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| author | Matt Ettus <matt@ettus.com> | 2010-05-20 00:34:35 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-20 00:34:35 -0700 |
| commit | 3b96b1f0f443acb9412b40592de5dc13e1f840d6 (patch) | |
| tree | 2d3ca681033828ba22cc1c3f3a3fbb630312ade9 /usrp2/top | |
| parent | 7a4080c082eb404864b3240a3460d03656697eb9 (diff) | |
| download | uhd-3b96b1f0f443acb9412b40592de5dc13e1f840d6.tar.gz uhd-3b96b1f0f443acb9412b40592de5dc13e1f840d6.tar.bz2 uhd-3b96b1f0f443acb9412b40592de5dc13e1f840d6.zip | |
put over/underrun on debug bus, remove high order address bits
Diffstat (limited to 'usrp2/top')
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 71b9b8712..48b5bd010 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -361,7 +361,8 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun }, + { EM_A[8:1] }, { EM_D } }; //assign debug = { phase[23:8], txsync, txblank, tx }; |