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-rw-r--r--host/lib/usrp/b200/b200_io_impl.cpp2
-rw-r--r--host/lib/usrp/gps_ctrl.cpp3
-rw-r--r--host/lib/usrp/x300/x300_impl.cpp16
-rw-r--r--host/lib/usrp/x300/x300_impl.hpp17
-rw-r--r--host/lib/usrp/x300/x300_radio_ctrl_impl.cpp17
-rw-r--r--host/lib/usrp/x300/x300_radio_ctrl_impl.hpp8
-rw-r--r--host/lib/usrp/x300/x300_regs.hpp2
7 files changed, 46 insertions, 19 deletions
diff --git a/host/lib/usrp/b200/b200_io_impl.cpp b/host/lib/usrp/b200/b200_io_impl.cpp
index 283091140..d1468332e 100644
--- a/host/lib/usrp/b200/b200_io_impl.cpp
+++ b/host/lib/usrp/b200/b200_io_impl.cpp
@@ -501,7 +501,7 @@ tx_streamer::sptr b200_impl::get_tx_stream(const uhd::stream_args_t &args_)
if (_tree->access<bool>("/mboards/0/auto_tick_rate").get()) {
set_auto_tick_rate(0, "", args.channels.size());
}
- check_streamer_args(args, this->get_tick_rate(), "RX");
+ check_streamer_args(args, this->get_tick_rate(), "TX");
boost::shared_ptr<sph::send_packet_streamer> my_streamer;
for (size_t stream_i = 0; stream_i < args.channels.size(); stream_i++)
diff --git a/host/lib/usrp/gps_ctrl.cpp b/host/lib/usrp/gps_ctrl.cpp
index bfc243d79..2c78b1834 100644
--- a/host/lib/usrp/gps_ctrl.cpp
+++ b/host/lib/usrp/gps_ctrl.cpp
@@ -1,5 +1,5 @@
//
-// Copyright 2010-2011,2014-2015 Ettus Research LLC
+// Copyright 2010-2011,2014-2016 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -135,7 +135,6 @@ private:
void update_cache() {
if(not gps_detected() or (_gps_type != GPS_TYPE_INTERNAL_GPSDO)) {
- UHD_MSG(error) << "get_stat(): unsupported GPS or no GPS detected";
return;
}
diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp
index 7f7fcad09..e4f6d6fb8 100644
--- a/host/lib/usrp/x300/x300_impl.cpp
+++ b/host/lib/usrp/x300/x300_impl.cpp
@@ -960,7 +960,12 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr)
BOOST_FOREACH(const rfnoc::block_id_t &id, radio_ids) {
rfnoc::x300_radio_ctrl_impl::sptr radio(get_block_ctrl<rfnoc::x300_radio_ctrl_impl>(id));
mb.radios.push_back(radio);
- radio->setup_radio(mb.zpu_i2c, mb.clock, dev_addr.has_key("self_cal_adc_delay"));
+ radio->setup_radio(
+ mb.zpu_i2c,
+ mb.clock,
+ dev_addr.has_key("ignore-cal-file"),
+ dev_addr.has_key("self_cal_adc_delay")
+ );
}
////////////////////////////////////////////////////////////////////
@@ -1440,11 +1445,6 @@ bool x300_impl::is_pps_present(mboard_members_t& mb)
* eeprom
**********************************************************************/
-void x300_impl::set_db_eeprom(i2c_iface::sptr i2c, const size_t addr, const uhd::usrp::dboard_eeprom_t &db_eeprom)
-{
- db_eeprom.store(*i2c, addr);
-}
-
void x300_impl::set_mb_eeprom(i2c_iface::sptr i2c, const mboard_eeprom_t &mb_eeprom)
{
i2c_iface::sptr eeprom16 = i2c->eeprom16();
@@ -1664,6 +1664,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
case X310_2943R_40MHz_PCIE_SSID_ADC_18:
case X310_2943R_120MHz_PCIE_SSID_ADC_18:
case X310_2944R_40MHz_PCIE_SSID_ADC_18:
+ case X310_2945R_PCIE_SSID_ADC_18:
case X310_2950R_40MHz_PCIE_SSID_ADC_18:
case X310_2950R_120MHz_PCIE_SSID_ADC_18:
case X310_2952R_40MHz_PCIE_SSID_ADC_18:
@@ -1671,6 +1672,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_pcie(const std::string& res
case X310_2953R_40MHz_PCIE_SSID_ADC_18:
case X310_2953R_120MHz_PCIE_SSID_ADC_18:
case X310_2954R_40MHz_PCIE_SSID_ADC_18:
+ case X310_2955R_PCIE_SSID_ADC_18:
mb_type = USRP_X310_MB; break;
default:
mb_type = UNKNOWN; break;
@@ -1721,6 +1723,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
case X310_2943R_40MHz_PCIE_SSID_ADC_18:
case X310_2943R_120MHz_PCIE_SSID_ADC_18:
case X310_2944R_40MHz_PCIE_SSID_ADC_18:
+ case X310_2945R_PCIE_SSID_ADC_18:
case X310_2950R_40MHz_PCIE_SSID_ADC_18:
case X310_2950R_120MHz_PCIE_SSID_ADC_18:
case X310_2952R_40MHz_PCIE_SSID_ADC_18:
@@ -1728,6 +1731,7 @@ x300_impl::x300_mboard_t x300_impl::get_mb_type_from_eeprom(const uhd::usrp::mbo
case X310_2953R_40MHz_PCIE_SSID_ADC_18:
case X310_2953R_120MHz_PCIE_SSID_ADC_18:
case X310_2954R_40MHz_PCIE_SSID_ADC_18:
+ case X310_2955R_PCIE_SSID_ADC_18:
mb_type = USRP_X310_MB; break;
default:
UHD_MSG(warning) << "X300 unknown product code in EEPROM: " << product_num << std::endl;
diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp
index d491e2bc0..ee42dcf3e 100644
--- a/host/lib/usrp/x300/x300_impl.hpp
+++ b/host/lib/usrp/x300/x300_impl.hpp
@@ -1,5 +1,5 @@
//
-// Copyright 2013-2015 Ettus Research LLC
+// Copyright 2013-2016 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -61,8 +61,8 @@ static const size_t X300_PCIE_MSG_NUM_FRAMES = 64;
static const size_t X300_PCIE_MAX_CHANNELS = 6;
static const size_t X300_PCIE_MAX_MUXED_XPORTS = 32;
-static const size_t X300_10GE_DATA_FRAME_MAX_SIZE = 8000; //bytes
-static const size_t X300_1GE_DATA_FRAME_MAX_SIZE = 1472; //bytes
+static const size_t X300_10GE_DATA_FRAME_MAX_SIZE = 8000; // CHDR packet size in bytes
+static const size_t X300_1GE_DATA_FRAME_MAX_SIZE = 1472; // CHDR packet size in bytes
static const size_t X300_ETH_MSG_FRAME_SIZE = uhd::transport::udp_simple::mtu; //bytes
static const double X300_THREAD_BUFFER_TIMEOUT = 0.1; // Time in seconds
@@ -72,8 +72,14 @@ static const size_t X300_ETH_DATA_NUM_FRAMES = 32;
static const double X300_DEFAULT_SYSREF_RATE = 10e6;
static const size_t X300_MAX_RATE_PCIE = 800000000; // bytes/s
-static const size_t X300_MAX_RATE_10GIGE = 800000000; // bytes/s
-static const size_t X300_MAX_RATE_1GIGE = 100000000; // bytes/s
+static const size_t X300_MAX_RATE_10GIGE = (size_t)( // bytes/s
+ 10e9 / 8 * // wire speed multiplied by percentage of packets that is sample data
+ ( float(X300_10GE_DATA_FRAME_MAX_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) /
+ float(X300_10GE_DATA_FRAME_MAX_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ )));
+static const size_t X300_MAX_RATE_1GIGE = (size_t)( // bytes/s
+ 10e9 / 8 * // wire speed multiplied by percentage of packets that is sample data
+ ( float(X300_1GE_DATA_FRAME_MAX_SIZE - uhd::usrp::DEVICE3_TX_MAX_HDR_LEN) /
+ float(X300_1GE_DATA_FRAME_MAX_SIZE + 8 /* UDP header */ + 20 /* Ethernet header length */ )));
#define X300_RADIO_DEST_PREFIX_TX 0
@@ -260,7 +266,6 @@ private:
bool wait_for_clk_locked(mboard_members_t& mb, boost::uint32_t which, double timeout);
bool is_pps_present(mboard_members_t& mb);
- void set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &);
void set_mb_eeprom(uhd::i2c_iface::sptr i2c, const uhd::usrp::mboard_eeprom_t &);
void check_fw_compat(const uhd::fs_path &mb_path, uhd::wb_iface::sptr iface);
diff --git a/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp b/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
index e1b724db6..e11548703 100644
--- a/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
+++ b/host/lib/usrp/x300/x300_radio_ctrl_impl.cpp
@@ -297,9 +297,14 @@ double x300_radio_ctrl_impl::get_output_samp_rate(size_t chan)
/****************************************************************************
* Radio control and setup
***************************************************************************/
-void x300_radio_ctrl_impl::setup_radio(uhd::i2c_iface::sptr zpu_i2c, x300_clock_ctrl::sptr clock, bool verbose)
+void x300_radio_ctrl_impl::setup_radio(
+ uhd::i2c_iface::sptr zpu_i2c,
+ x300_clock_ctrl::sptr clock,
+ bool ignore_cal_file,
+ bool verbose)
{
_self_cal_adc_capture_delay(verbose);
+ _ignore_cal_file = ignore_cal_file;
////////////////////////////////////////////////////////////////////
// create RF frontend interfacing
@@ -322,8 +327,8 @@ void x300_radio_ctrl_impl::setup_radio(uhd::i2c_iface::sptr zpu_i2c, x300_clock_
//Add to tree
_tree->create<dboard_eeprom_t>(db_path / EEPROM_PATHS[i])
.set(_db_eeproms[addr])
- .add_coerced_subscriber(boost::bind(&dboard_eeprom_t::store,
- _db_eeproms[addr], boost::ref(*zpu_i2c), (BASE_ADDR | addr)));
+ .add_coerced_subscriber(boost::bind(&x300_radio_ctrl_impl::_set_db_eeprom,
+ this, zpu_i2c, (BASE_ADDR | addr), _1));
}
//create a new dboard interface
@@ -855,6 +860,12 @@ void x300_radio_ctrl_impl::_check_adc(const boost::uint32_t val)
}
}
+void x300_radio_ctrl_impl::_set_db_eeprom(i2c_iface::sptr i2c, const size_t addr, const uhd::usrp::dboard_eeprom_t &db_eeprom)
+{
+ db_eeprom.store(*i2c, addr);
+ _db_eeproms[addr] = db_eeprom;
+}
+
/****************************************************************************
* Helpers
***************************************************************************/
diff --git a/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp b/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
index 770519eba..46540a0c7 100644
--- a/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
+++ b/host/lib/usrp/x300/x300_radio_ctrl_impl.hpp
@@ -73,7 +73,11 @@ public:
/*! Set up the radio. No API calls may be made before this one.
*/
void setup_radio(
- uhd::i2c_iface::sptr zpu_i2c, x300_clock_ctrl::sptr clock, bool verbose);
+ uhd::i2c_iface::sptr zpu_i2c,
+ x300_clock_ctrl::sptr clock,
+ bool ignore_cal_file,
+ bool verbose
+ );
void reset_codec();
@@ -152,6 +156,8 @@ private:
void _check_adc(const boost::uint32_t val);
+ void _set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &);
+
void set_rx_fe_corrections(const uhd::fs_path &db_path, const uhd::fs_path &rx_fe_corr_path, const double lo_freq);
void set_tx_fe_corrections(const uhd::fs_path &db_path, const uhd::fs_path &tx_fe_corr_path, const double lo_freq);
diff --git a/host/lib/usrp/x300/x300_regs.hpp b/host/lib/usrp/x300/x300_regs.hpp
index c5ed1460b..80d275949 100644
--- a/host/lib/usrp/x300/x300_regs.hpp
+++ b/host/lib/usrp/x300/x300_regs.hpp
@@ -104,6 +104,7 @@ static const uint32_t X310_2942R_120MHz_PCIE_SSID_ADC_18 = 0x785C;
static const uint32_t X310_2943R_40MHz_PCIE_SSID_ADC_18 = 0x7855;
static const uint32_t X310_2943R_120MHz_PCIE_SSID_ADC_18 = 0x785D;
static const uint32_t X310_2944R_40MHz_PCIE_SSID_ADC_18 = 0x7856;
+static const uint32_t X310_2945R_PCIE_SSID_ADC_18 = 0x78EF;
static const uint32_t X310_2950R_40MHz_PCIE_SSID_ADC_18 = 0x7857;
static const uint32_t X310_2950R_120MHz_PCIE_SSID_ADC_18 = 0x785E;
static const uint32_t X310_2952R_40MHz_PCIE_SSID_ADC_18 = 0x7858;
@@ -111,6 +112,7 @@ static const uint32_t X310_2952R_120MHz_PCIE_SSID_ADC_18 = 0x785F;
static const uint32_t X310_2953R_40MHz_PCIE_SSID_ADC_18 = 0x7859;
static const uint32_t X310_2953R_120MHz_PCIE_SSID_ADC_18 = 0x7860;
static const uint32_t X310_2954R_40MHz_PCIE_SSID_ADC_18 = 0x785A;
+static const uint32_t X310_2955R_PCIE_SSID_ADC_18 = 0x78F0;
static const uint32_t FPGA_X3xx_SIG_VALUE = 0x58333030;
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-30 02:46:51 +0000