diff options
Diffstat (limited to 'fpga/usrp3/top')
| -rw-r--r-- | fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile index bf4922c21..956c1f211 100644 --- a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile @@ -25,11 +25,12 @@ DESIGN_SRCS = $(abspath ../../e310_io.v) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = e310_io_tb +# Define toplevel module +SIM_TOP = e310_io_tb glbl SIM_SRCS = \ -$(abspath e310_io_tb.sv) +$(abspath e310_io_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile |