diff options
9 files changed, 68 insertions, 89 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile index d574c9a01..b63685ef7 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # @@ -7,57 +7,43 @@ #------------------------------------------------- # Top-of-Makefile #------------------------------------------------- -# Define BASE_DIR to point to the "top" dir -BASE_DIR = $(abspath ../../../../top) -# Include viv_sim_preamble after defining BASE_DIR +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +BASE_DIR = ../../../../top +# Include viv_sim_preample after defining BASE_DIR include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak #------------------------------------------------- -# IP Specific -#------------------------------------------------- -# If simulation contains IP, define the IP_DIR and point -# it to the base level IP directory -LIB_IP_DIR = $(BASE_DIR)/../lib/ip - -# Include makefiles and sources for all IP components -# *after* defining the LIB_IP_DIR -#include $(LIB_IP_DIR)/axi_fft/Makefile.inc -#include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc -include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc -include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc -include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs - -DESIGN_SRCS += $(abspath \ -$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \ -$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ -$(COREGEN_DSP_SRCS) \ -) - -#------------------------------------------------- # Design Specific #------------------------------------------------- -# Include makefiles and sources for the DUT and its dependencies +# Include makefiles and sources for the DUT and its +# dependencies. include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc +include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc +include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs include Makefile.srcs DESIGN_SRCS += $(abspath \ $(RFNOC_CORE_SRCS) \ $(RFNOC_UTIL_SRCS) \ +$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \ +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ +$(COREGEN_DSP_SRCS) \ $(RFNOC_BLOCK_DDC_SRCS) \ ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = rfnoc_block_ddc_tb - -# Add test bench, user design under test, and -# additional user created files +MODELSIM_LIBS += unimacro_ver +SIM_TOP = rfnoc_block_ddc_tb glbl SIM_SRCS = \ -$(COREGEN_DSP_SRCS) \ -$(abspath rfnoc_block_ddc_tb.sv) +$(abspath $(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd) \ +$(abspath $(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd) \ +$(abspath rfnoc_block_ddc_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs index 28663f03c..08676d2e6 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile index 6d1da3d60..c632e52f6 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # @@ -7,56 +7,51 @@ #------------------------------------------------- # Top-of-Makefile #------------------------------------------------- -# Define BASE_DIR to point to the "top" dir -BASE_DIR = $(abspath ../../../../top) -# Include viv_sim_preamble after defining BASE_DIR +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +BASE_DIR = ../../../../top +# Include viv_sim_preample after defining BASE_DIR include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak #------------------------------------------------- -# IP Specific +# Design Specific #------------------------------------------------- -# If simulation contains IP, define the IP_DIR and point -# it to the base level IP directory -LIB_IP_DIR = $(BASE_DIR)/../lib/ip - -# Include makefiles and sources for all IP components -# *after* defining the LIB_IP_DIR +# Include makefiles and sources for the DUT and its +# dependencies. +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs include $(LIB_IP_DIR)/axi_hb47/Makefile.inc include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs +include Makefile.srcs DESIGN_SRCS += $(abspath \ +$(RFNOC_CORE_SRCS) \ +$(RFNOC_UTIL_SRCS) \ $(LIB_IP_AXI_HB47_SRCS) \ $(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \ $(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ $(COREGEN_DSP_SRCS) \ -) - -#------------------------------------------------- -# Design Specific -#------------------------------------------------- -# Include makefiles and sources for the DUT and its dependencies -include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs -include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs -include Makefile.srcs - -DESIGN_SRCS += $(abspath \ -$(RFNOC_CORE_SRCS) \ -$(RFNOC_UTIL_SRCS) \ $(RFNOC_BLOCK_DUC_SRCS) \ ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = rfnoc_block_duc_tb - -# Add test bench, user design under test, and -# additional user created files +SIM_TOP = rfnoc_block_duc_tb glbl SIM_SRCS = \ -$(abspath rfnoc_block_duc_tb.sv) +$(abspath $(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd) \ +$(abspath $(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd) \ +$(abspath $(IP_BUILD_DIR)/axi_hb47/sim/axi_hb47.vhd) \ +$(abspath modelsim_proj/axi_hb47.mif) \ +$(abspath rfnoc_block_duc_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ + +# Copy the .mif file so ModelSim can find it +$(abspath modelsim_proj/axi_hb47.mif) : $(LIB_IP_AXI_HB47_OUTS) + mkdir -p modelsim_proj + cp $(abspath $(IP_BUILD_DIR)/axi_hb47/axi_hb47.mif) $(abspath modelsim_proj/axi_hb47.mif) #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs index 8f534082c..bd3051949 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile index 868246fbd..14869d7d9 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # @@ -45,13 +45,10 @@ $(RFNOC_OOT_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = rfnoc_block_fft_tb - -# Add test bench, user design under test, and -# additional user created files +SIM_TOP = rfnoc_block_fft_tb glbl SIM_SRCS = \ -$(abspath rfnoc_block_fft_tb.sv) +$(abspath rfnoc_block_fft_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs index 21ba967f2..b2d823453 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # diff --git a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile index b2cc6908e..d40b6f341 100644 --- a/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile +++ b/fpga/usrp3/lib/rfnoc/xport_sv/eth_interface_tb/Makefile @@ -30,13 +30,8 @@ include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs -BUILD_IP_DIR = $(abspath $(BASE_DIR)/x300/build-ip/xc7k410tffg900-2) - -IP_SRC = \ -$(abspath $(BUILD_IP_DIR)/fifo_short_2clk/fifo_short_2clk_sim_netlist.v) -# Xilinx IP wants lots of libraries -MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm -MODELSIM_ARGS += glbl -t 1fs +IP_DIR = $(BASE_DIR)/x300/ip +include $(BASE_DIR)/x300/ip/fifo_short_2clk/Makefile.inc DESIGN_SRCS = $(abspath \ eth_ifc_synth_test.sv \ @@ -51,22 +46,26 @@ $(RFNOC_XPORT_SRCS) \ $(RFNOC_XPORT_SV_SRCS) \ $(RFNOC_XBAR_SRCS) \ $(RFNOC_CORE_SRCS) \ -$(IP_SRC) \ +$(IP_FIFO_SHORT_2CLK_SRCS) \ ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module +MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4 +MODELSIM_ARGS += glbl -t 1fs +# Define toplevel module TB_TOP_MODULE ?= eth_ifc_all_tb #TB_TOP_MODULE ?= eth_ifc_synth_test SIM_TOP = $(TB_TOP_MODULE) SIM_SRCS = \ +$(abspath $(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v) \ $(abspath eth_ifc_tb.sv) \ -$(abspath $(TB_TOP_MODULE).sv) +$(abspath $(TB_TOP_MODULE).sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ -# supressing the following worthless reminder. +# Suppressing the following worthless reminder. #* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] - # Extra checking for conflicts with always_comb and always_latch variables is done at vopt time SVLOG_ARGS = -suppress 2583 -keep_delta diff --git a/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile index f0cdb3704..eb764749f 100644 --- a/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile +++ b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile @@ -25,13 +25,14 @@ $(DSP_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = mult_add_clip_tb +# Define toplevel module +SIM_TOP = mult_add_clip_tb glbl # Add test bench, user design under test, and # additional user created files SIM_SRCS = $(abspath \ mult_add_clip_tb.sv \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ ) # MODELSIM_USER_DO = $(abspath wave.do) diff --git a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile index bf4922c21..956c1f211 100644 --- a/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile +++ b/fpga/usrp3/top/e31x/sim/e310_io_tb/Makefile @@ -25,11 +25,12 @@ DESIGN_SRCS = $(abspath ../../e310_io.v) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = e310_io_tb +# Define toplevel module +SIM_TOP = e310_io_tb glbl SIM_SRCS = \ -$(abspath e310_io_tb.sv) +$(abspath e310_io_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile |