1 files changed, 0 insertions, 21 deletions
diff --git a/fpga/usrp3/top/b200/catcap_tb.build b/fpga/usrp3/top/b200/catcap_tb.build
deleted file mode 100755
index 827ab0628..000000000
--- a/fpga/usrp3/top/b200/catcap_tb.build
+++ /dev/null
@@ -1,21 +0,0 @@
-
-#!/bin/sh
-
-rm -rf isim* 
-rm -rf catcap_tb
-rm -rf fuse*
-\
-#     --sourcelibdir ../../models \
-
-vlogcomp \
-    --sourcelibext .v \
-    --sourcelibdir ../../coregen \
-    --sourcelibdir ../../control_lib \
-    --sourcelibdir . \
-    --sourcelibdir $XILINX/verilog/src \
-    --sourcelibdir $XILINX/verilog/src/unisims \
-    --work work \
-    catcap_tb.v
-
- 
-fuse -o catcap_tb catcap_tb
-\ No newline at end of file