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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/top/b200/catcap_tb.build | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/top/b200/catcap_tb.build')
| -rwxr-xr-x | fpga/usrp3/top/b200/catcap_tb.build | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/fpga/usrp3/top/b200/catcap_tb.build b/fpga/usrp3/top/b200/catcap_tb.build deleted file mode 100755 index 827ab0628..000000000 --- a/fpga/usrp3/top/b200/catcap_tb.build +++ /dev/null @@ -1,21 +0,0 @@ - -#!/bin/sh - -rm -rf isim* -rm -rf catcap_tb -rm -rf fuse* -\ -# --sourcelibdir ../../models \ - -vlogcomp \ - --sourcelibext .v \ - --sourcelibdir ../../coregen \ - --sourcelibdir ../../control_lib \ - --sourcelibdir . \ - --sourcelibdir $XILINX/verilog/src \ - --sourcelibdir $XILINX/verilog/src/unisims \ - --work work \ - catcap_tb.v - - -fuse -o catcap_tb catcap_tb
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