diff options
Diffstat (limited to 'fpga/usrp3/tools/scripts/viv_ip_xci_editor.py')
| -rw-r--r-- | fpga/usrp3/tools/scripts/viv_ip_xci_editor.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py index b749b76da..8648c8b5e 100644 --- a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py +++ b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py @@ -57,7 +57,11 @@ def main(): if args.action == 'read_partid': print(xci_info['DEVICE'] + '/' + xci_info['PACKAGE'] + '/' + xci_info['SPEEDGRADE'] + '/' + xci_info['TEMPERATURE_GRADE'] + '/' + xci_info['SILICON_REVISION']) if args.action == 'read_part': - print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE']) + # The UltraScale+ RFSoC family ids are expected diferently in Vivado, a '-' must separate each property. + if xci_info['ARCHITECTURE'] == "zynquplusRFSOC": + print(xci_info['DEVICE'] + "-" + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'] + "-" + xci_info['TEMPERATURE_GRADE']) + else: + print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE']) elif args.action == 'retarget': # Write a new XCI file with modified target info if not os.path.isdir(args.output_dir): |