diff options
Diffstat (limited to 'fpga/usrp3/lib')
79 files changed, 1572 insertions, 470 deletions
diff --git a/fpga/usrp3/lib/control/Makefile.srcs b/fpga/usrp3/lib/control/Makefile.srcs index e0ad8a942..9e44579ad 100644 --- a/fpga/usrp3/lib/control/Makefile.srcs +++ b/fpga/usrp3/lib/control/Makefile.srcs @@ -23,4 +23,5 @@ axi_forwarding_cam.v \ axi_test_vfifo.v \ dram_2port.v \ cvita_uart.v \ +serial_to_settings.v \ )) diff --git a/fpga/usrp3/lib/control/arb_qualify_master.v b/fpga/usrp3/lib/control/arb_qualify_master.v index df17fac57..e9c67b7ac 100644 --- a/fpga/usrp3/lib/control/arb_qualify_master.v +++ b/fpga/usrp3/lib/control/arb_qualify_master.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // This module forms the qualification engine for a single master as diff --git a/fpga/usrp3/lib/control/axi_crossbar.v b/fpga/usrp3/lib/control/axi_crossbar.v index a408f69f0..c64931b6e 100644 --- a/fpga/usrp3/lib/control/axi_crossbar.v +++ b/fpga/usrp3/lib/control/axi_crossbar.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `define LOG2(N) (\ N < 2 ? 0 : \ diff --git a/fpga/usrp3/lib/control/axi_crossbar_tb.v b/fpga/usrp3/lib/control/axi_crossbar_tb.v index 1994cb352..b14f859d4 100644 --- a/fpga/usrp3/lib/control/axi_crossbar_tb.v +++ b/fpga/usrp3/lib/control/axi_crossbar_tb.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `timescale 1 ps / 1 ps module axi_crossbar_tb; diff --git a/fpga/usrp3/lib/control/axi_fifo_header.v b/fpga/usrp3/lib/control/axi_fifo_header.v index ceac8e324..1a0d13cd0 100644 --- a/fpga/usrp3/lib/control/axi_fifo_header.v +++ b/fpga/usrp3/lib/control/axi_fifo_header.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // This module is connected to the output port of an AXI4-STREAM FIFO that is used to move packetized data. diff --git a/fpga/usrp3/lib/control/axi_forwarding_cam.v b/fpga/usrp3/lib/control/axi_forwarding_cam.v index 2f28b5640..cb6e82684 100644 --- a/fpga/usrp3/lib/control/axi_forwarding_cam.v +++ b/fpga/usrp3/lib/control/axi_forwarding_cam.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // This module implements a highly customized TCAM that enbales forwarding diff --git a/fpga/usrp3/lib/control/axi_slave_mux.v b/fpga/usrp3/lib/control/axi_slave_mux.v index 1a307aba5..3f2424584 100644 --- a/fpga/usrp3/lib/control/axi_slave_mux.v +++ b/fpga/usrp3/lib/control/axi_slave_mux.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/control/binary_encoder.v b/fpga/usrp3/lib/control/binary_encoder.v new file mode 100644 index 000000000..e13a8174b --- /dev/null +++ b/fpga/usrp3/lib/control/binary_encoder.v @@ -0,0 +1,42 @@ + +`define LOG2(N) (\ + N < 2 ? 0 : \ + N < 4 ? 1 : \ + N < 8 ? 2 : \ + N < 16 ? 3 : \ + N < 32 ? 4 : \ + N < 64 ? 5 : \ + N < 128 ? 6 : \ + N < 256 ? 7 : \ + N < 512 ? 8 : \ + N < 1024 ? 9 : \ + 10) + + module binary_encoder + #( + parameter SIZE = 16 + ) + ( + input [SIZE-1:0] in, + output [`LOG2(SIZE)-1:0] out + ); + + genvar m,n; + + generate + // Loop enough times to represent the total number of input bits as an encoded value + for (m = 0; m <= `log2(SIZE-1); m = m + 1) begin: expand_or_tree + wire [SIZE-1:0] encoding; + // Build enable mask by iterating through every input bit. + for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit + assign encoding[n] = n[m]; + end + // OR tree for this output bit with appropraite bits enabled. + assign out[m] = |(encoding & in); + end + endgenerate +endmodule // binary_encoder + + + +
\ No newline at end of file diff --git a/fpga/usrp3/lib/control/cvita_uart.v b/fpga/usrp3/lib/control/cvita_uart.v index cbb272fc2..e0d4697ce 100644 --- a/fpga/usrp3/lib/control/cvita_uart.v +++ b/fpga/usrp3/lib/control/cvita_uart.v @@ -2,7 +2,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //create a compressed vita based uart data interface diff --git a/fpga/usrp3/lib/control/gpio_atr.v b/fpga/usrp3/lib/control/gpio_atr.v index 9c707e52a..16449a711 100644 --- a/fpga/usrp3/lib/control/gpio_atr.v +++ b/fpga/usrp3/lib/control/gpio_atr.v @@ -2,7 +2,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module gpio_atr diff --git a/fpga/usrp3/lib/control/por_gen.v b/fpga/usrp3/lib/control/por_gen.v index 0e4fcd88a..89dc93d82 100644 --- a/fpga/usrp3/lib/control/por_gen.v +++ b/fpga/usrp3/lib/control/por_gen.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module por_gen diff --git a/fpga/usrp3/lib/control/ram_2port.v b/fpga/usrp3/lib/control/ram_2port.v index 434af0ff3..ab93157a4 100644 --- a/fpga/usrp3/lib/control/ram_2port.v +++ b/fpga/usrp3/lib/control/ram_2port.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/control/reset_sync.v b/fpga/usrp3/lib/control/reset_sync.v index da284e62e..3a58c0a5f 100644 --- a/fpga/usrp3/lib/control/reset_sync.v +++ b/fpga/usrp3/lib/control/reset_sync.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/control/serial_to_settings.v b/fpga/usrp3/lib/control/serial_to_settings.v new file mode 100644 index 000000000..53e112a62 --- /dev/null +++ b/fpga/usrp3/lib/control/serial_to_settings.v @@ -0,0 +1,111 @@ + + +module serial_to_settings + ( + input clk, + input reset, + // Serial signals (async) + input scl, + input sda, + // Settngs bus out + output reg set_stb, + output reg [7:0] set_addr, + output reg [31:0] set_data + ); + + reg [2:0] state; + + localparam SEARCH = 3'h0; + localparam ADDRESS = 3'h1; + localparam DATA = 3'h2; + localparam STOP1 = 3'h3; + localparam STOP2 = 3'h4; + + reg scl_pre_reg, scl_reg, scl_reg2; + reg sda_pre_reg, sda_reg, sda_reg2; + reg [4:0] counter; + + + always @(posedge clk) begin + scl_reg2 <= scl_reg; + scl_reg <= scl_pre_reg; + scl_pre_reg <= scl; + sda_reg2 <= sda_reg; + sda_reg <= sda_pre_reg; + sda_pre_reg <= sda; + end + + + always @(posedge clk) + if (reset) begin + state <= SEARCH; + counter <= 0; + set_addr <= 0; + set_data <= 0; + set_stb <= 0; + end else begin + case(state) + // + // Search for I2C like start indication: SDA goes low whilst clock is high. + // + SEARCH: begin + set_stb <= 0; + // Look for START. + if (scl_reg && scl_reg2 && !sda_reg && sda_reg2) begin + state <= ADDRESS; + counter <= 0; + end + end + // + // Count 8 Address bits. + // Master changes SDA on falling edge of SCL, we sample on the rising edge. + // + ADDRESS: begin + if (scl_reg && !scl_reg2) begin + set_addr[7:0] <= {set_addr[6:0],sda_reg}; + if (counter == 7) begin + state <= DATA; + counter <= 0; + end else + counter <= counter + 1; + end + end + // + // Count 32 data bits. + // Master changes SDA on falling edge of SCL, we sample on the rising edge. + // + DATA: begin + if (scl_reg && !scl_reg2) begin + set_data[31:0] <= {set_data[30:0],sda_reg}; + if (counter == 31) begin + state <= STOP1; + counter <= 0; + end else + counter <= counter + 1; + end + end + // + // Looks for rising SCL edge before STOP bit. + // + STOP1: begin + if (scl_reg && !scl_reg2) begin + state <= STOP2; + end + end + // + // Looks for STOP bit + // + STOP2: begin + if (scl_reg && scl_reg2 && sda_reg && !sda_reg2) begin + state <= SEARCH; + counter <= 0; + set_stb <= 1; + end + end + + endcase // case(state) + end // else: !if(reset) + + + +endmodule // serial_to_settings diff --git a/fpga/usrp3/lib/control/serial_to_settings_tb.v b/fpga/usrp3/lib/control/serial_to_settings_tb.v new file mode 100644 index 000000000..8111c115e --- /dev/null +++ b/fpga/usrp3/lib/control/serial_to_settings_tb.v @@ -0,0 +1,54 @@ + + +module serial_to_settings_tb(); + + + + reg clk; + reg reset; + + wire scl; + wire sda; + wire set_stb; + wire [7:0] set_addr; + wire [31:0] set_data; + + // + // These registers optionaly used + // to drive nets through procedural assignments in test bench. + // These drivers default to tri-stated. + // + reg scl_r; + reg sda_r; + + assign scl = scl_r; + assign sda = sda_r; + + initial + begin + scl_r <= 1'bz; + sda_r <= 1'bz; + end + + + + serial_to_settings serial_to_settings_i + ( + .clk(clk), + .reset(reset), + // Serial signals (async) + .scl(scl), + .sda(sda), + // Settngs bus out + .set_stb(set_stb), + .set_addr(set_addr), + .set_data(set_data) + ); + + + // + // Bring in a simulation script here + // + `include "simulation_script.v" + +endmodule
\ No newline at end of file diff --git a/fpga/usrp3/lib/control/setting_reg.v b/fpga/usrp3/lib/control/setting_reg.v index 1664f54e2..e9c1c73ac 100644 --- a/fpga/usrp3/lib/control/setting_reg.v +++ b/fpga/usrp3/lib/control/setting_reg.v @@ -1,7 +1,19 @@ // // Copyright 2011-2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //---------------------------------------------------------------------- //-- A settings register is a peripheral for the settings register bus. diff --git a/fpga/usrp3/lib/control/settings_bus_crossclock.v b/fpga/usrp3/lib/control/settings_bus_crossclock.v index 2a6e7e7ef..de74f67ee 100644 --- a/fpga/usrp3/lib/control/settings_bus_crossclock.v +++ b/fpga/usrp3/lib/control/settings_bus_crossclock.v @@ -1,7 +1,19 @@ // // Copyright 2011-2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/control/simple_i2c_core.v b/fpga/usrp3/lib/control/simple_i2c_core.v index 47f1ac82a..9c61de8fb 100644 --- a/fpga/usrp3/lib/control/simple_i2c_core.v +++ b/fpga/usrp3/lib/control/simple_i2c_core.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Simple I2C core diff --git a/fpga/usrp3/lib/control/simple_spi_core.v b/fpga/usrp3/lib/control/simple_spi_core.v index a18e00709..b94515e40 100644 --- a/fpga/usrp3/lib/control/simple_spi_core.v +++ b/fpga/usrp3/lib/control/simple_spi_core.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Simple SPI core, the simplest, yet complete spi core I can think of diff --git a/fpga/usrp3/lib/dsp/acc.v b/fpga/usrp3/lib/dsp/acc.v index 86b68512f..d5fc4b910 100644 --- a/fpga/usrp3/lib/dsp/acc.v +++ b/fpga/usrp3/lib/dsp/acc.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module acc diff --git a/fpga/usrp3/lib/dsp/add2.v b/fpga/usrp3/lib/dsp/add2.v index 124f9d6ca..dcca84fd3 100644 --- a/fpga/usrp3/lib/dsp/add2.v +++ b/fpga/usrp3/lib/dsp/add2.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module add2 diff --git a/fpga/usrp3/lib/dsp/add2_and_round.v b/fpga/usrp3/lib/dsp/add2_and_round.v index 9d0914414..7c347527c 100644 --- a/fpga/usrp3/lib/dsp/add2_and_round.v +++ b/fpga/usrp3/lib/dsp/add2_and_round.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module add2_and_round diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v index cb20a3c1b..5c783bda3 100644 --- a/fpga/usrp3/lib/dsp/add2_and_round_reg.v +++ b/fpga/usrp3/lib/dsp/add2_and_round_reg.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module add2_and_round_reg diff --git a/fpga/usrp3/lib/dsp/add2_reg.v b/fpga/usrp3/lib/dsp/add2_reg.v index 3ac93ae2e..58d822a61 100644 --- a/fpga/usrp3/lib/dsp/add2_reg.v +++ b/fpga/usrp3/lib/dsp/add2_reg.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module add2_reg diff --git a/fpga/usrp3/lib/dsp/cic_dec_shifter.v b/fpga/usrp3/lib/dsp/cic_dec_shifter.v index efc54c106..aa5ac895b 100644 --- a/fpga/usrp3/lib/dsp/cic_dec_shifter.v +++ b/fpga/usrp3/lib/dsp/cic_dec_shifter.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/fpga/usrp3/lib/dsp/cic_decim.v b/fpga/usrp3/lib/dsp/cic_decim.v index feb785de8..e6b6e9590 100644 --- a/fpga/usrp3/lib/dsp/cic_decim.v +++ b/fpga/usrp3/lib/dsp/cic_decim.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/fpga/usrp3/lib/dsp/cic_int_shifter.v b/fpga/usrp3/lib/dsp/cic_int_shifter.v index ff5a30d6a..18587fa8b 100644 --- a/fpga/usrp3/lib/dsp/cic_int_shifter.v +++ b/fpga/usrp3/lib/dsp/cic_int_shifter.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/fpga/usrp3/lib/dsp/cic_interp.v b/fpga/usrp3/lib/dsp/cic_interp.v index 608c2d448..9b6928aa1 100644 --- a/fpga/usrp3/lib/dsp/cic_interp.v +++ b/fpga/usrp3/lib/dsp/cic_interp.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/fpga/usrp3/lib/dsp/cic_strober.v b/fpga/usrp3/lib/dsp/cic_strober.v index 269b85f75..40d76bdd9 100644 --- a/fpga/usrp3/lib/dsp/cic_strober.v +++ b/fpga/usrp3/lib/dsp/cic_strober.v @@ -3,7 +3,19 @@ // // Copyright (C) 2008 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module cic_strober diff --git a/fpga/usrp3/lib/dsp/clip.v b/fpga/usrp3/lib/dsp/clip.v index 294c5e8ba..3e6b3a2e2 100644 --- a/fpga/usrp3/lib/dsp/clip.v +++ b/fpga/usrp3/lib/dsp/clip.v @@ -4,7 +4,19 @@ // // Copyright (C) 2008 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Clipping "macro", keeps the bottom bits diff --git a/fpga/usrp3/lib/dsp/clip_reg.v b/fpga/usrp3/lib/dsp/clip_reg.v index ab9a5b79d..9098fd5b8 100644 --- a/fpga/usrp3/lib/dsp/clip_reg.v +++ b/fpga/usrp3/lib/dsp/clip_reg.v @@ -4,7 +4,19 @@ // // Copyright (C) 2008 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Clipping "macro", keeps the bottom bits diff --git a/fpga/usrp3/lib/dsp/cordic_stage.v b/fpga/usrp3/lib/dsp/cordic_stage.v index 7019ead52..641ff9108 100644 --- a/fpga/usrp3/lib/dsp/cordic_stage.v +++ b/fpga/usrp3/lib/dsp/cordic_stage.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo); diff --git a/fpga/usrp3/lib/dsp/cordic_z24.v b/fpga/usrp3/lib/dsp/cordic_z24.v index d9e983ccd..51b074a33 100644 --- a/fpga/usrp3/lib/dsp/cordic_z24.v +++ b/fpga/usrp3/lib/dsp/cordic_z24.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003, 2007 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo ); diff --git a/fpga/usrp3/lib/dsp/ddc_chain.v b/fpga/usrp3/lib/dsp/ddc_chain.v index 365175bf1..b802416c1 100644 --- a/fpga/usrp3/lib/dsp/ddc_chain.v +++ b/fpga/usrp3/lib/dsp/ddc_chain.v @@ -1,7 +1,19 @@ // // Copyright 2011-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //! The USRP digital down-conversion chain diff --git a/fpga/usrp3/lib/dsp/duc_chain.v b/fpga/usrp3/lib/dsp/duc_chain.v index 06c87bd34..6c2381c90 100644 --- a/fpga/usrp3/lib/dsp/duc_chain.v +++ b/fpga/usrp3/lib/dsp/duc_chain.v @@ -1,7 +1,19 @@ // // Copyright 2011-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //! The USRP digital up-conversion chain diff --git a/fpga/usrp3/lib/dsp/hb_dec.v b/fpga/usrp3/lib/dsp/hb_dec.v index 65c771ca7..8d21c21c0 100644 --- a/fpga/usrp3/lib/dsp/hb_dec.v +++ b/fpga/usrp3/lib/dsp/hb_dec.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Final halfband decimator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] diff --git a/fpga/usrp3/lib/dsp/hb_interp.v b/fpga/usrp3/lib/dsp/hb_interp.v index c0914255c..d89046db7 100644 --- a/fpga/usrp3/lib/dsp/hb_interp.v +++ b/fpga/usrp3/lib/dsp/hb_interp.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // First halfband iterpolator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] diff --git a/fpga/usrp3/lib/dsp/round.v b/fpga/usrp3/lib/dsp/round.v index 7ecc10ff7..26d5a4cf4 100644 --- a/fpga/usrp3/lib/dsp/round.v +++ b/fpga/usrp3/lib/dsp/round.v @@ -4,7 +4,19 @@ // // Copyright (C) 2011 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Rounding "macro" diff --git a/fpga/usrp3/lib/dsp/round_reg.v b/fpga/usrp3/lib/dsp/round_reg.v index c8c77f518..6f2e974d7 100644 --- a/fpga/usrp3/lib/dsp/round_reg.v +++ b/fpga/usrp3/lib/dsp/round_reg.v @@ -4,7 +4,19 @@ // // Copyright (C) 2008 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // // Rounding "macro" diff --git a/fpga/usrp3/lib/dsp/rx_dcoffset.v b/fpga/usrp3/lib/dsp/rx_dcoffset.v index f74b0f1a0..04d7795c0 100644 --- a/fpga/usrp3/lib/dsp/rx_dcoffset.v +++ b/fpga/usrp3/lib/dsp/rx_dcoffset.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v index 7c85920aa..eae67faf2 100644 --- a/fpga/usrp3/lib/dsp/sign_extend.v +++ b/fpga/usrp3/lib/dsp/sign_extend.v @@ -4,7 +4,19 @@ // // Copyright (C) 2003 Matt Ettus // - +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // diff --git a/fpga/usrp3/lib/dsp/small_hb_dec.v b/fpga/usrp3/lib/dsp/small_hb_dec.v index fc776c2d7..c05a48b81 100644 --- a/fpga/usrp3/lib/dsp/small_hb_dec.v +++ b/fpga/usrp3/lib/dsp/small_hb_dec.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] diff --git a/fpga/usrp3/lib/dsp/small_hb_int.v b/fpga/usrp3/lib/dsp/small_hb_int.v index 4b03b5d0c..ff17069cc 100644 --- a/fpga/usrp3/lib/dsp/small_hb_int.v +++ b/fpga/usrp3/lib/dsp/small_hb_int.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v index bbd8ac1c9..6df226e8f 100644 --- a/fpga/usrp3/lib/dsp/srl.v +++ b/fpga/usrp3/lib/dsp/srl.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module srl diff --git a/fpga/usrp3/lib/fifo/axi_fifo.v b/fpga/usrp3/lib/fifo/axi_fifo.v index 2f42fc181..efc8f02f1 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo.v +++ b/fpga/usrp3/lib/fifo/axi_fifo.v @@ -1,7 +1,19 @@ // // Copyright 2012-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Block RAM AXI fifo diff --git a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v index f9f7beb88..889bc0f9a 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo_2clk.v +++ b/fpga/usrp3/lib/fifo/axi_fifo_2clk.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Special case SIZE <= 5 uses a short fifo diff --git a/fpga/usrp3/lib/fifo/axi_fifo_short.v b/fpga/usrp3/lib/fifo/axi_fifo_short.v index e13993199..db34af082 100644 --- a/fpga/usrp3/lib/fifo/axi_fifo_short.v +++ b/fpga/usrp3/lib/fifo/axi_fifo_short.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // 32 word FIFO with AXI4-STREAM interface. diff --git a/fpga/usrp3/lib/fifo/axi_packet_gate.v b/fpga/usrp3/lib/fifo/axi_packet_gate.v index 6d10a8cf4..e1f999250 100644 --- a/fpga/usrp3/lib/fifo/axi_packet_gate.v +++ b/fpga/usrp3/lib/fifo/axi_packet_gate.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Hold packets in fifo until they are complete. This prevents slowly-built packets // from clogging up the downstream. This block will hold up to 255 packets. diff --git a/fpga/usrp3/lib/fifo/monitor_axi_fifo.v b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v index f5d73455f..504296e92 100644 --- a/fpga/usrp3/lib/fifo/monitor_axi_fifo.v +++ b/fpga/usrp3/lib/fifo/monitor_axi_fifo.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // This module is instantiated in parallel with a FIFO with AXI4-STREAM interfaces. diff --git a/fpga/usrp3/lib/fifo/shortfifo.v b/fpga/usrp3/lib/fifo/shortfifo.v index fbf92e2ed..c7c916375 100644 --- a/fpga/usrp3/lib/fifo/shortfifo.v +++ b/fpga/usrp3/lib/fifo/shortfifo.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module shortfifo diff --git a/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v index cf3a221b7..1e4a429a3 100644 --- a/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v +++ b/fpga/usrp3/lib/gpif2/fifo64_to_gpif2.v @@ -1,7 +1,19 @@ // // Copyright 2012-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module fifo64_to_gpif2 #( diff --git a/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v index f332a6ab3..93aa6041f 100644 --- a/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v +++ b/fpga/usrp3/lib/gpif2/gpif2_slave_fifo32.v @@ -1,7 +1,19 @@ // // Copyright 2011-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// ////////////////////////////////////////////////////////////////////////////////// @@ -23,8 +35,11 @@ module gpif2_slave_fifo32 parameter END_WITH_COMMA = 0 ) - (// GPIF signals - input gpif_clk, input gpif_rst, input gpif_enb, + ( + // GPIF signals + input gpif_clk, + input gpif_rst, + input gpif_enb, inout [31:0] gpif_d, input [3:0] gpif_ctl, output reg sloe, @@ -33,15 +48,18 @@ module gpif2_slave_fifo32 output slcs, output reg pktend, output reg [1:0] fifoadr, - // FIFO interfaces - input fifo_clk, input fifo_rst, - + input fifo_clk, + input fifo_rst, + // TX Data interface to DSP output [63:0] tx_tdata, output tx_tlast, output tx_tvalid, input tx_tready, + // RX Data interface to DSP input [63:0] rx_tdata, input rx_tlast, input rx_tvalid, output rx_tready, + // Incomming control interface output [63:0] ctrl_tdata, output ctrl_tlast, output ctrl_tvalid, input ctrl_tready, + // Outgoing control interface input [63:0] resp_tdata, input resp_tlast, input resp_tvalid, output resp_tready, - + // Debug Signals output [31:0] debug ); @@ -49,8 +67,6 @@ module gpif2_slave_fifo32 wire ctrl_tx_fifo_nearly_full, data_tx_fifo_nearly_full; wire ctrl_tx_fifo_has_space, data_tx_fifo_has_space; - - wire [159:0] debug_tx_data, debug_tx_ctrl; assign slcs = 1'b0; @@ -137,14 +153,19 @@ module gpif2_slave_fifo32 end // - // now wait here for 8 clock cycles before transitioning to STATE_THINK. - // We stay in this state if no local FIFO's can proceed at this point. + // If the current thread we are pointing at (fifoadr) can not immediately proceed + // then quickly move to the next thread. Once we are pointing at a thread that can proceed locally + // wait for 8 clock cycles to allow fifoadr to propogate to FX3, and corresponding flag state to + // propogate back to FPGA and through resampling flops. At this point transition to STATE_THINK + // to evaluate remote flag. // STATE_WAIT: begin + // Current thread can proceed locally if (local_fifo_ready) begin idle_cycles <= idle_cycles + 1'b1; if (idle_cycles == 3'b111) state <= STATE_THINK; end + // ....move onto next thread. else begin idle_cycles <= 3'b0; fifoadr <= fifoadr + 2'b1; @@ -154,10 +175,10 @@ module gpif2_slave_fifo32 // // If there is a read to start, assert SLRD and SLOE and transition to STATE_READ. // If there is a write to perform, set flags that says there is the possibility to do at least - // one write (wr_one) and transition to STATE_WRITE + // one write (wr_one) and transition to STATE_WRITE. + // If the FX3 has nothing ready for this thread return immediately to STATE_IDLE. // STATE_THINK: begin - if (EP_READY1 && read_ready_go) begin state <= STATE_READ; slrd <= 0; @@ -215,13 +236,17 @@ module gpif2_slave_fifo32 //Priority encoding for the the next address to service: //The next address to service is based on the readiness //of the internal fifos and last serviced fairness metric. +/* -----\/----- EXCLUDED -----\/----- always @(posedge gpif_clk) next_addr <= - ((ctrl_rx_tvalid && last_addr != ADDR_CTRL_RX)? ADDR_CTRL_RX : - ((ctrl_tx_fifo_has_space && last_addr != ADDR_CTRL_TX)? ADDR_CTRL_TX : - ((data_rx_tvalid && last_addr != ADDR_DATA_RX)? ADDR_DATA_RX : - ((data_tx_fifo_has_space && last_addr != ADDR_DATA_TX)? ADDR_DATA_TX : + ((ctrl_rx_tvalid && (last_addr != ADDR_CTRL_RX))? ADDR_CTRL_RX : + ((ctrl_tx_fifo_has_space && (last_addr != ADDR_CTRL_TX))? ADDR_CTRL_TX : + ((data_rx_tvalid && (last_addr != ADDR_DATA_RX))? ADDR_DATA_RX : + ((data_tx_fifo_has_space && (last_addr != ADDR_DATA_TX))? ADDR_DATA_TX : (fifoadr + 2'b1) )))); + -----/\----- EXCLUDED -----/\----- */ + always @(posedge gpif_clk) next_addr <= (fifoadr + 2'b1); + //Help the FPGA search to only look for addrs that the FPGA is ready for assign local_fifo_ready = @@ -268,7 +293,7 @@ module gpif2_slave_fifo32 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .fifo_nearly_full(data_tx_fifo_nearly_full), .fifo_has_space(data_tx_fifo_has_space), .o_tdata(tx_tdata), .o_tlast(tx_tlast), .o_tvalid(tx_tvalid), .o_tready(tx_tready), - .bus_error(tx_bus_error), .debug(debug_tx_data) + .bus_error(tx_bus_error), .debug() ); // //////////////////////////////////////////// @@ -290,7 +315,7 @@ module gpif2_slave_fifo32 .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .fifo_nearly_full(ctrl_tx_fifo_nearly_full), .fifo_has_space(ctrl_tx_fifo_has_space), .o_tdata(ctrl_tdata), .o_tlast(ctrl_tlast), .o_tvalid(ctrl_tvalid), .o_tready(ctrl_tready), - .bus_error(ctrl_bus_error), .debug(debug_tx_ctrl) + .bus_error(ctrl_bus_error), .debug() ); // //////////////////////////////////////////////////////////////////// @@ -306,70 +331,6 @@ module gpif2_slave_fifo32 // //////////////////////////////////////////// // DEBUG - wire [31:0] debug0 = { - sloe, slrd, slwr, pktend, fifoadr, EP_READY, EP_WMARK, //8 - state, //4 - data_tx_tvalid, data_tx_tready, data_rx_tvalid, data_rx_tready, //4 - gpif_d[15:0] //16 - }; - - reg [31:0] debug_reg0; - reg [31:0] debug_reg1; - reg [31:0] debug_reg2; - always @(posedge gpif_clk) debug_reg0 <= debug0; - always @(posedge gpif_clk) debug_reg1 <= debug_reg0; - always @(posedge gpif_clk) debug_reg2 <= debug_reg1; - assign debug = debug_reg2; - - wire [37:0] debug_resp = { - resp_tlast, // 37 - resp_tready, // 36 - resp_tvalid, // 35 - ctrl_rx_tlast, // 34 - ctrl_rx_tready, // 33 - ctrl_rx_tvalid, // 32 - ctrl_rx_tdata // 31:0 - }; - - - reg [255:0] debug1,debug2; - - always @(posedge gpif_clk) debug1 <= {debug_resp,debug_tx_ctrl,debug0}; - always @(posedge gpif_clk) debug2 <= debug1; - - - - wire [35:0] CONTROL0,CONTROL1; - /* - chipscope_ila_32 chipscope_ila_32( - .CONTROL(CONTROL0), // INOUT BUS [35:0] - .CLK(gpif_clk), // IN - .TRIG0(debug2) // IN BUS [31:0] - ); - - chipscope_ila_128 chipscope_ila_128( - .CONTROL(CONTROL1), // INOUT BUS [35:0] - .CLK(fifo_clk), // IN - .TRIG0({debug4,debug6}) // IN BUS [31:0] - ); - - - chipscope_ila_256 chipscope_ila_256( - .CONTROL(CONTROL0), // INOUT BUS [35:0] - .CLK(gpif_clk), // IN - .TRIG0(debug2) // IN BUS [31:0] - ); - chipscope_ila_32 chipscope_ila_32_2( - .CONTROL(CONTROL1), // INOUT BUS [35:0] - .CLK(gpif_clk), // IN - .TRIG0(32'd0) // IN BUS [31:0] - ); - - chipscope_icon chipscope_icon( - .CONTROL0(CONTROL0), // INOUT BUS [35:0] - .CONTROL1(CONTROL1) // INOUT BUS [35:0] - ); - */ endmodule // gpif2_slave_fifo32 diff --git a/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v index 3d60c7326..c6d50a59d 100644 --- a/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v +++ b/fpga/usrp3/lib/gpif2/gpif2_to_fifo64.v @@ -1,118 +1,136 @@ // // Copyright 2012-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module gpif2_to_fifo64 -#( + #( parameter FIFO_SIZE = 9 -) -( - //input interface - input gpif_clk, input gpif_rst, - input [31:0] i_tdata, - input i_tlast, - input i_tvalid, - output i_tready, - output fifo_has_space, - output fifo_nearly_full, - - //output fifo interface - input fifo_clk, input fifo_rst, - output [63:0] o_tdata, - output o_tlast, - output o_tvalid, - input o_tready, - - output bus_error, - output [159:0] debug -); - - wire [31:0] int_tdata; - wire int_tlast; - wire int_tvalid, int_tready; - - wire [31:0] int0_tdata; wire int0_tlast, int0_tvalid, int0_tready; - - //this fifo provides a space signal so we know a burst is possible - localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8; - wire [15:0] space; - - - assign fifo_has_space = space >= (1 << BURST_SIZE); - assign fifo_nearly_full = (space < 6); // 5 spaces left. - - axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo - ( - .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(), - .o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied() - ); - axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff + ) ( - .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), - .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space), - .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied() - ); - - reg input_write_error; - - always @(posedge gpif_clk) input_write_error <= i_tvalid & ~i_tready; - + //input interface + input gpif_clk, + input gpif_rst, + input [31:0] i_tdata, + input i_tlast, + input i_tvalid, + output i_tready, + output fifo_has_space, + output fifo_nearly_full, - wire [31:0] chk_tdata; - wire chk_tlast; - wire chk_tvalid, chk_tready; + //output fifo interface + input fifo_clk, + input fifo_rst, + output [63:0] o_tdata, + output o_tlast, + output o_tvalid, + input o_tready, - axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo - ( - .reset(fifo_rst | gpif_rst), - .i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready), - .o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready) - ); - - wire [31:0] o32_tdata; - wire o32_tlast; - wire o32_tvalid, o32_tready; - - //reframes a tlast from the vita header - and drops bad packets - //* - gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker - ( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready), - .o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready), - .bus_error(bus_error), .debug(debug[63:0]) - ); - //*/ - //assign o32_tdata = chk_tdata; - //assign o32_tlast = chk_tlast; - //assign o32_tvalid = chk_tvalid; - //assign chk_tready = o32_tready; - - axi_fifo32_to_fifo64 fifo32_to_fifo64 - ( - .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), - .i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready), - .o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready) - ); - - assign debug[159:64] = { - fifo_nearly_full, // 146 - space[9:0], // 145:136 - input_write_error, // 135 - int_tlast, // 134 - int_tready, // 133 - int_tvalid, // 132 - i_tlast, // 131 - i_tready, // 130 - fifo_has_space, // 129 - i_tvalid, // 128 - int_tdata[31:0], // 127:96 - i_tdata[31:0] // 95:64 - }; + output bus_error, + output [31:0] debug + ); + wire [31:0] int_tdata; + wire int_tlast; + wire int_tvalid, int_tready; + + wire [31:0] int0_tdata; + wire int0_tlast, int0_tvalid, int0_tready; + + // + // Generate flags that show if initial FIFO's can accept a maximum sized burst from the FX3 + // or if the FIFO is about to fill. + // + localparam BURST_SIZE = (FIFO_SIZE < 8)? FIFO_SIZE : 8; + wire [15:0] space; + assign fifo_has_space = space >= (1 << BURST_SIZE); + assign fifo_nearly_full = (space < 6); // 5 spaces left. + + // + // This FIFO is provdied purely to easy FPGA timing closure as data is comming from I/O pins. + // + axi_fifo #(.WIDTH(33), .SIZE(0)) ingress_timing_fifo + ( + .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), + .i_tdata({i_tlast, i_tdata}), .i_tvalid(i_tvalid), .i_tready(i_tready), .space(), + .o_tdata({int0_tlast, int0_tdata}), .o_tvalid(int0_tvalid), .o_tready(int0_tready), .occupied() + ); + + // + // This FIFO provides space to accept a single burst from FX3 and it's fullness drives flags to GPIF2 logic + // + axi_fifo #(.WIDTH(33), .SIZE(BURST_SIZE)) min_read_buff + ( + .clk(gpif_clk), .reset(gpif_rst), .clear(1'b0), + .i_tdata({int0_tlast, int0_tdata}), .i_tvalid(int0_tvalid), .i_tready(int0_tready), .space(space), + .o_tdata({int_tlast, int_tdata}), .o_tvalid(int_tvalid), .o_tready(int_tready), .occupied() + ); + + // + // This logic allows signals to cross from the GPIF2 clock domain to the BUS clock domain. + // It may now be obselete if bus_clk and gpif_clk are merged + // + wire [31:0] chk_tdata; + wire chk_tlast; + wire chk_tvalid, chk_tready; + + axi_fifo_2clk #(.WIDTH(33), .SIZE(0/*SRL*/)) cross_clock_fifo + ( + .reset(fifo_rst | gpif_rst), + .i_aclk(gpif_clk), .i_tdata({int_tlast, int_tdata}), .i_tvalid(int_tvalid), .i_tready(int_tready), + .o_aclk(fifo_clk), .o_tdata({chk_tlast, chk_tdata}), .o_tvalid(chk_tvalid), .o_tready(chk_tready) + ); + + // + // Performs basic tests on incomming packets such as testing if size on the wire patches + // the internal size field. Uses axi_packet_gate internally so can back pressure upstream if + // packet needs to be dropped. + // + wire [31:0] o32_tdata; + wire o32_tlast; + wire o32_tvalid, o32_tready; + + gpif2_error_checker #(.SIZE(FIFO_SIZE)) checker + ( + .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), + .i_tdata(chk_tdata), .i_tlast(chk_tlast), .i_tvalid(chk_tvalid), .i_tready(chk_tready), + .o_tdata(o32_tdata), .o_tlast(o32_tlast), .o_tvalid(o32_tvalid), .o_tready(o32_tready), + .bus_error(bus_error), .debug() + ); - + //assign o32_tdata = chk_tdata; + //assign o32_tlast = chk_tlast; + //assign o32_tvalid = chk_tvalid; + //assign chk_tready = o32_tready; + + // + // Convert 32bit AXIS bus to 64bit + // + axi_fifo32_to_fifo64 fifo32_to_fifo64 + ( + .clk(fifo_clk), .reset(fifo_rst), .clear(1'b0), + .i_tdata(o32_tdata), .i_tuser(2'b0/*always 32 bits*/), .i_tlast(o32_tlast), .i_tvalid(o32_tvalid), .i_tready(o32_tready), + .o_tdata(o_tdata), .o_tuser(/*ignored cuz vita has len*/), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready) + ); + + + ///////////////////////////////////////////// + // + // Debug logic only + // + ///////////////////////////////////////////// + endmodule //fifo_to_gpif2 diff --git a/fpga/usrp3/lib/packet_proc/cvita_chunker.v b/fpga/usrp3/lib/packet_proc/cvita_chunker.v index cbc34d00a..c74c387d8 100644 --- a/fpga/usrp3/lib/packet_proc/cvita_chunker.v +++ b/fpga/usrp3/lib/packet_proc/cvita_chunker.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Quantize cvita packets to a configurable quantum value. o_tlast and // i_tready will be held off until the entire quantized packet is xferred. // If quantum is changed, it is the responsibility of the client to clear diff --git a/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v b/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v index 08f46d72a..1771fb7ab 100644 --- a/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v +++ b/fpga/usrp3/lib/packet_proc/cvita_chunker_tb.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `timescale 500ps/1ps diff --git a/fpga/usrp3/lib/packet_proc/cvita_dechunker.v b/fpga/usrp3/lib/packet_proc/cvita_dechunker.v index 2ad873305..2d8c94ab5 100644 --- a/fpga/usrp3/lib/packet_proc/cvita_dechunker.v +++ b/fpga/usrp3/lib/packet_proc/cvita_dechunker.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module cvita_dechunker # ( parameter PAD_VALUE = 64'hFFFFFFFF_FFFFFFFF diff --git a/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v b/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v index 198eb4c40..0bffd348e 100644 --- a/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v +++ b/fpga/usrp3/lib/packet_proc/cvita_dechunker_tb.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `timescale 500ps/1ps diff --git a/fpga/usrp3/lib/packet_proc/eth_dispatch.v b/fpga/usrp3/lib/packet_proc/eth_dispatch.v index b600a1533..7068d5a77 100644 --- a/fpga/usrp3/lib/packet_proc/eth_dispatch.v +++ b/fpga/usrp3/lib/packet_proc/eth_dispatch.v @@ -72,6 +72,7 @@ module eth_dispatch output xo_tvalid, input xo_tready, // Debug + output [2:0] debug_flags, output [31:0] debug ); @@ -93,6 +94,7 @@ module eth_dispatch // // Small RAM stores packet header during parsing. // + // IJB consider changing HEADER_RAM_SIZE to 7 localparam HEADER_RAM_SIZE = 9; (*ram_style="distributed"*) reg [68:0] header_ram [HEADER_RAM_SIZE-1:0]; @@ -100,7 +102,7 @@ module eth_dispatch reg drop_this_packet; wire header_done = (header_ram_addr == HEADER_RAM_SIZE-1); - reg fwd_input; + reg fwd_input; // reg [63:0] in_tdata_reg; @@ -112,10 +114,8 @@ module eth_dispatch wire [3:0] out_tuser; wire [63:0] out_tdata; - - // - // Output AXI-STream interface to VITA Radio Core + // Output AXI-Stream interface to VITA Radio Core wire [63:0] vita_pre_tdata; wire [3:0] vita_pre_tuser; wire vita_pre_tlast; @@ -147,10 +147,6 @@ module eth_dispatch reg is_icmp_no_fwd; reg is_chdr; - - - - // // Settings regs // @@ -417,12 +413,14 @@ module eth_dispatch end 7: begin // Look for a possible CHDR header string + // IJB. NOTE this is not a good test for a CHDR packet, we perhaps don;t need this state anyhow. if (in_tdata_reg[63:32] != 32'h0) is_chdr <= 1'b1; end 8: begin // Check VRT Stream ID // ADD THIS HERE. + // IJB. Perhaps delete this state. end endcase // case (header_ram_addr) end // if (in_tvalid && in_tready) @@ -452,9 +450,12 @@ module eth_dispatch (out_tready && fwd_input); + // // Because we can forward to both the ZPU and XO FIFO's concurrently // we have to make sure both can accept data in the same cycle. // This makes it possible for either destination to block the other. + // Make sure (both) destination(s) can accept data before passing it. + // assign xo_pre_tvalid = out_tvalid && ((state == FORWARD_XO) || ((state == FORWARD_ZPU_AND_XO) && zpu_pre_tready)); @@ -524,6 +525,9 @@ module eth_dispatch .space(), .occupied() ); + + assign debug_flags = {vita_pre_tready,xo_pre_tready,zpu_pre_tready}; + /* -----\/----- EXCLUDED -----\/----- diff --git a/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v b/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v index ecc7d1025..27207058e 100644 --- a/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v +++ b/fpga/usrp3/lib/packet_proc/eth_dispatch_tb.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `timescale 1 ps / 1 ps module eth_dispatch_tb(); diff --git a/fpga/usrp3/lib/packet_proc/eth_interface.v b/fpga/usrp3/lib/packet_proc/eth_interface.v index 083badfea..e6fa3252d 100644 --- a/fpga/usrp3/lib/packet_proc/eth_interface.v +++ b/fpga/usrp3/lib/packet_proc/eth_interface.v @@ -21,7 +21,8 @@ module eth_interface // ZPU output [63:0] e2z_tdata, output [3:0] e2z_tuser, output e2z_tlast, output e2z_tvalid, input e2z_tready, input [63:0] z2e_tdata, input [3:0] z2e_tuser, input z2e_tlast, input z2e_tvalid, output z2e_tready, - + // Debug + output [31:0] debug_flags, output [31:0] debug ); @@ -36,7 +37,12 @@ module eth_interface wire [63:0] epg_tdata_int; wire [3:0] epg_tuser_int; wire epg_tlast_int, epg_tvalid_int, epg_tready_int; - + + // + // Packet gate ensures on entire ingressing packet is buffered before feeding it downstream so that it bursts + // efficiently internally without holding resources allocted for longer than optimal. This also means that an upstream + // error discovered in the packet can allow the packet to be destroyed here, before it gets deeper into the USRP. + // axi_packet_gate #(.WIDTH(68), .SIZE(10)) packet_gater //holds 8K pkts (.clk(clk), .reset(reset), .clear(clear), @@ -47,10 +53,14 @@ module eth_interface .o_tdata({epg_tuser_int, epg_tdata_int}), .o_tlast(epg_tlast_int), .o_tvalid(epg_tvalid_int), .o_tready(epg_tready_int)); + // + // Based on programmed rules, parse network headers and decide which internal destination(s) this packet will be forwarded to. + // wire [63:0] e2z_tdata_int; wire [3:0] e2z_tuser_int; wire e2z_tlast_int, e2z_tvalid_int, e2z_tready_int; - + wire [2:0] dispatch_debug_flags; + eth_dispatch #(.BASE(BASE+8)) eth_dispatch (.clk(clk), .reset(reset), .clear(clear), .set_stb(set_stb), .set_addr(set_addr) , .set_data(set_data), @@ -58,8 +68,11 @@ module eth_interface .vita_tdata(e2v_tdata), .vita_tlast(e2v_tlast), .vita_tvalid(e2v_tvalid), .vita_tready(e2v_tready), .zpu_tdata(e2z_tdata_int), .zpu_tuser(e2z_tuser_int), .zpu_tlast(e2z_tlast_int), .zpu_tvalid(e2z_tvalid_int), .zpu_tready(e2z_tready_int), .xo_tdata(xo_tdata), .xo_tuser(xo_tuser), .xo_tlast(xo_tlast), .xo_tvalid(xo_tvalid), .xo_tready(xo_tready), // to other eth port - .debug(debug)); + .debug_flags(dispatch_debug_flags),.debug(debug)); + // + // ZPU can be slow to respond (relative to packet wirespeed) so extra buffer for packets destined there so it doesn't back up. + // axi_fifo #(.WIDTH(69),.SIZE(ZPU_FIFOSIZE)) zpu_fifo (.clk(clk), .reset(reset), .clear(clear), .i_tdata({e2z_tlast_int,e2z_tuser_int,e2z_tdata_int}), .i_tvalid(e2z_tvalid_int), .i_tready(e2z_tready_int), @@ -110,4 +123,38 @@ module eth_interface .i_tdata({eth_tx_tlast_int,eth_tx_tuser_int,eth_tx_tdata_int}), .i_tvalid(eth_tx_tvalid_int), .i_tready(eth_tx_tready_int), .o_tdata({eth_tx_tlast,eth_tx_tuser,eth_tx_tdata}), .o_tvalid(eth_tx_tvalid), .o_tready(eth_tx_tready)); + + // + // Provide instrumentation so that abnormal FIFO conditions can be identifed. + // +/* -----\/----- EXCLUDED -----\/----- + + setting_reg #(.my_addr(BASE+15), .awidth(16), .width(1)) sr_reset_fifo_debug + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_debug_flags)); + + always @(posedge clk) + if (reset) + debug_flags <= 0; + else if (clear_debug_flags) + debug_flags <= 0; + else + debug_flags <= debug_flags | {eth_rx_tuser[3], + ~eth_tx_tready_int, + ~xi_tready, + ~v2e_tready, + ~e2z_tready_int, + ~eth_rx_tready, + ~dispatch_debug_flags[2:0]}; + -----/\----- EXCLUDED -----/\----- */ + + assign debug_flags = {eth_rx_tuser[3], + ~eth_tx_tready_int, + ~xi_tready, + ~v2e_tready, + ~e2z_tready_int, + ~eth_rx_tready, + ~dispatch_debug_flags[2:0]}; + + endmodule // eth_interface diff --git a/fpga/usrp3/lib/timing/time_compare.v b/fpga/usrp3/lib/timing/time_compare.v index 272c41b65..eded432e1 100644 --- a/fpga/usrp3/lib/timing/time_compare.v +++ b/fpga/usrp3/lib/timing/time_compare.v @@ -1,7 +1,19 @@ // // Copyright 2011-2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // 64 bits worth of ticks diff --git a/fpga/usrp3/lib/timing/time_transfer_tb.v b/fpga/usrp3/lib/timing/time_transfer_tb.v index af1207605..288540702 100644 --- a/fpga/usrp3/lib/timing/time_transfer_tb.v +++ b/fpga/usrp3/lib/timing/time_transfer_tb.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// `timescale 1ns / 1ps diff --git a/fpga/usrp3/lib/timing/timekeeper.v b/fpga/usrp3/lib/timing/timekeeper.v index 627472094..f20c48d4b 100644 --- a/fpga/usrp3/lib/timing/timekeeper.v +++ b/fpga/usrp3/lib/timing/timekeeper.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module timekeeper #(parameter BASE = 0) diff --git a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v index 2ae61a32d..6a415dae5 100644 --- a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v +++ b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v index c91d9cbd1..39ee2ccc9 100644 --- a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v +++ b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v @@ -1,221 +1,260 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module chdr_16sc_to_12sc #(parameter BASE=0) - ( input set_stb, input [7:0] set_addr, input [31:0] set_data, - //left side of device - input clk, input reset, + ( + // Clocks and resets + input clk, + input reset, + // Settings bus + input set_stb, + input [7:0] set_addr, + input [31:0] set_data, + // Input CHDR bus input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready, - //right side of device - output reg [63:0] o_tdata = 0, + // Output CHDR bus + output reg [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready, - + // Debug output [31:0] debug - ); - - wire chdr_has_hdr = 1'b1; - wire chdr_has_time = i_tdata[61]; - wire chdr_has_tlr = 1'b0; - - wire [11:0] imag0; - wire [11:0] real0; - wire [11:0] imag1; - wire [11:0] real1; - wire [11:0] imag2; - wire [11:0] real2; - - - - wire [16:0] round_i0; - wire [16:0] round_r0; - wire [16:0] round_i1; - wire [16:0] round_r1; - wire [16:0] round_i2; - wire [16:0] round_r2; - -//pipiline registers - - reg [11:0] imag0_out; - reg [11:0] real0_out; - reg [11:0] imag1_out; - reg [11:0] real1_out; - - reg [15:0] len_data; - - //chdr length calculations - wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8; - wire [15:0] in_samples = i_tdata[47:32] - chdr_header_lines; - wire [15:0] samples = (in_samples*3) >> 2; - wire [15:0] chdr_payload_lines = samples + chdr_header_lines; - - - reg needs_exline = 0; - reg in_exline = 0; - - - wire set_sid; - wire [15:0] my_newhome; - + ); + + wire chdr_has_time = i_tdata[61]; + + wire [11:0] q0; + wire [11:0] i0; + wire [11:0] q1; + wire [11:0] i1; + wire [11:0] q2; + wire [11:0] i2; + + wire [16:0] round_q0; + wire [16:0] round_i0; + wire [16:0] round_q1; + wire [16:0] round_i1; + wire [16:0] round_q2; + wire [16:0] round_i2; + + // Pipeline registers + reg [11:0] q0_out; + reg [11:0] i0_out; + reg [11:0] q1_out; + reg [11:0] i1_out; + + // CHDR has either 8 bytes of header or 16 if VITA time is included. + wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8; + // Calculate size of samples input in bytes by taking CHDR size filed and subtracting header length. + wire [15:0] sample_byte_count_in = i_tdata[47:32] - chdr_header_lines; + // Calculate size of samples to be output by taking input size and scaling by 3/4 + wire [15:0] sample_byte_count_out = (sample_byte_count_in*3) >> 2; + // Calculate size of output CHDR packet by adding back header size to new payload size. + wire [15:0] output_chdr_pkt_size = sample_byte_count_out + chdr_header_lines; + + reg needs_extra_line; + reg in_extra_line; + + wire set_sid; + wire [15:0] new_sid_dst; + setting_reg #(.my_addr(BASE), .width(17)) new_destination (.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data), - .out({set_sid, my_newhome[15:0]})); - - //state machine - - localparam HEADER = 3'd0; // IDLE - localparam TIME = 3'd1; - localparam LINE_ODD_ZERO = 3'd2; - localparam LINE_EVEN_ONE = 3'd3; - localparam LINE_ODD_TWO = 3'd4; - localparam REG_STATE = 3'd5; - - reg [2:0] state; - - - - always @(posedge clk) begin - if (reset) begin - state <= HEADER; - needs_exline <= 0; - in_exline <= 0; - end - - - else if ((o_tvalid && o_tready) || (i_tready && i_tvalid)) case(state) - - - HEADER: begin - - needs_exline <= (in_samples[4:2] == 3 || in_samples[4:2] == 4 || in_samples[4:2] == 6); - state <= (i_tdata[61])? TIME: REG_STATE; - - end - - TIME: begin - state <= (i_tlast) ? HEADER: REG_STATE; - end - - REG_STATE: begin - if (i_tlast & !needs_exline || in_exline) begin - state <= HEADER; - in_exline <= 0; - end - else if (i_tlast & needs_exline) begin - state <= LINE_EVEN_ONE; - in_exline <= 1; - - end - else - state <= LINE_EVEN_ONE; - end - - - LINE_EVEN_ONE: begin - if (i_tlast & !needs_exline || in_exline) begin - state <= HEADER; - in_exline <= 0; - end - else if (i_tlast & needs_exline) begin - state <= LINE_ODD_TWO; - in_exline <= 1; - - end - else - state <= LINE_ODD_TWO; - end - - - - - LINE_ODD_TWO: begin - if (i_tlast & !needs_exline || in_exline) begin - state <= HEADER; - in_exline <= 0; - end - else if (i_tlast & needs_exline) begin - state <= LINE_ODD_ZERO; - in_exline <= 1; - - end - else - state <= LINE_ODD_ZERO; - end - - LINE_ODD_ZERO: begin - if (i_tlast & !needs_exline || in_exline) begin - state <= HEADER; - in_exline <= 0; - end - else if (i_tlast & needs_exline) begin - state <= REG_STATE; - in_exline <= 1; - end - else - state <= REG_STATE; - end - - default: state <= HEADER; - - endcase - end - - assign round_i0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008); - assign round_r0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008); - - assign imag0 = (round_i0[16] == 0 && round_i0[15] == 1)?(12'h7FF):(round_i0[16] == 1 && round_i0[15] == 0)? (12'h800):(round_i0[15:4]); - - assign real0 = (round_r0[16] == 0 && round_r0[15] == 1)?(12'h7FF):(round_r0[16] == 1 && round_r0[15] == 0)? (12'h800):(round_r0[15:4]); - - assign round_i1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008); - assign round_r1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008); - - assign imag1 = (round_i1[16] == 0 && round_i1[15] == 1)?(12'h7FF):(round_i1[16] == 1 && round_i1[15] == 0)? (12'h800):(round_i1[15:4]); - - assign real1 = (round_r1[16] == 0 && round_r1[15] == 1)?(12'h7FF):(round_r1[16] == 1 && round_r1[15] == 0)? (12'h800):(round_r1[15:4]); - - - - + .out({set_sid, new_sid_dst[15:0]})); + // state machine + + localparam HEADER = 3'd0; + localparam TIME = 3'd1; + localparam SAMPLE1 = 3'd2; + localparam SAMPLE2 = 3'd3; + localparam SAMPLE3 = 3'd4; + localparam SAMPLE4 = 3'd5; + + reg [2:0] state; + + always @(posedge clk) + if (reset) begin + state <= HEADER; + needs_extra_line <= 0; + in_extra_line <= 0; + end else begin + case(state) + // + // Process Header line of input packet or idle in this state waiting for new packet. + // If the the input packet has SAMPLE_COUNT MODULO 8 == 3 or 4 or 6 then when tlast is asserted we will need one more + // output cycle to finish outputing processed samples. + // + HEADER: begin + if (o_tready && i_tvalid) + begin + needs_extra_line <= (sample_byte_count_in[4:2] == 3 || sample_byte_count_in[4:2] == 4 || sample_byte_count_in[4:2] == 6); + // If the input packet had time, then add time to output packet + state <= (i_tdata[61])? TIME: SAMPLE1; + end + end + // + // Process time field of input packet + // + TIME: begin + if (o_tready && i_tvalid) + begin + // If we get a premature end of line go back to searching for start of new packet. + state <= (i_tlast) ? HEADER: SAMPLE1; + end + end + // + // Process line of sample data from input packet. + // Not yet enough data to prepare first of three repeating output lines + // unless this the last line of a packet when the lats output line + // is composed of data from one or both samples in this input packet. + // + SAMPLE1: begin + if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin + // We can finish this packet immediately. + state <= HEADER; + in_extra_line <= 0; + end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin + // We still need one more output line to drain all samples into this packet. + // (SHOULD NOT BE POSSIBLE TO GET HERE!) + state <= SAMPLE2; + in_extra_line <= 1; + end else if (o_tready && i_tvalid) + state <= SAMPLE2; + end + // + // First of three repeating output line patterns + // + SAMPLE2: begin + if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin + // We can finish this packet immediately. + state <= HEADER; + in_extra_line <= 0; + end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin + // We still need one more output line to drain all samples into this packet. + state <= SAMPLE3; + in_extra_line <= 1; + end else if (o_tready && i_tvalid) + state <= SAMPLE3; + end + // + // Second of three repeating output line patterns + // + SAMPLE3: begin + if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin + // We can finish this packet immediately. + state <= HEADER; + in_extra_line <= 0; + end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin + // We still need one more output line to drain all samples into this packet. + state <= SAMPLE4; + in_extra_line <= 1; + end else if (o_tready && i_tvalid) + state <= SAMPLE4; + end + // + // Third of three repeating output line patterns + // + SAMPLE4: begin + if ((i_tlast && !needs_extra_line && o_tready && i_tvalid) || (in_extra_line && o_tready)) begin + // We can finish this packet immediately. + state <= HEADER; + in_extra_line <= 0; + end else if (i_tlast && needs_extra_line && o_tready && i_tvalid) begin + // We still need one more output line to drain all samples into this packet. + // (SHOULD NOT BE POSSIBLE TO GET HERE!!) + state <= SAMPLE1; + in_extra_line <= 1; + end else if (o_tready && i_tvalid) + state <= SAMPLE1; + end + // + // Should never get here. + // + default: state <= HEADER; + + endcase + end + + + // Add rounding value into 16bit samples before trunctaion + assign round_q0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008); + assign round_i0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008); + // Truncate with saturation to 12bits precision. + assign q0 = (round_q0[16:15] == 2'b01) ? 12'h7FF : ((round_q0[16:15] == 2'b10) ? 12'h800 : round_q0[15:4]); + assign i0 = (round_i0[16:15] == 2'b01) ? 12'h7FF : ((round_i0[16:15] == 2'b10) ? 12'h800 : round_i0[15:4]); + // Add rounding value into 16bit samples before trunctaion + assign round_q1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008); + assign round_i1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008); + // Truncate with saturation to 12bits precision. + assign q1 = (round_q1[16:15] == 2'b01) ? 12'h7FF : ((round_q1[16:15] == 2'b10) ? 12'h800 : round_q1[15:4]); + assign i1 = (round_i1[16:15] == 2'b01) ? 12'h7FF : ((round_i1[16:15] == 2'b10) ? 12'h800 : round_i1[15:4]); + + // + // Keep values from current input line to populate fields in next cycles output line + // always @(posedge clk) if (i_tvalid && o_tready) begin - imag0_out <= imag0; - real0_out <= real0; - imag1_out <= imag1; - real1_out <= real1; + q0_out <= q0; + i0_out <= i0; + q1_out <= q1; + i1_out <= i1; end - - + // + // Mux Output data + // always @(*) case(state) - - HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines, - set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]}; - TIME: o_tdata <= i_tdata; - - - REG_STATE: o_tdata <= {imag0,real0,imag1, real1, 16'b0}; - - LINE_EVEN_ONE: o_tdata <= {imag0_out, real0_out, imag1_out, real1_out, imag0, real0[11:8]}; - LINE_ODD_TWO: o_tdata <= {real0_out[7:0], imag1_out, real1_out, imag0, real0,imag1[11:4]}; - LINE_ODD_ZERO: o_tdata <= {imag1_out[3:0], real1_out, imag0, real0, imag1, real1}; - - default : o_tdata <= i_tdata; - endcase - - assign o_tvalid =((in_exline) || (state != REG_STATE & i_tvalid) || (i_tlast & i_tvalid & !needs_exline)); - assign i_tready = (o_tready & !in_exline)||(state == REG_STATE && !i_tlast); - assign o_tlast = (needs_exline)? in_exline: i_tlast; - - + // Populate header with CHDR fields + HEADER: o_tdata = {i_tdata[63:48], output_chdr_pkt_size, + set_sid ? {i_tdata[15:0], new_sid_dst[15:0]}:i_tdata[31:0]}; + // Add 64bit VITA time to packet + TIME: o_tdata = i_tdata; + // Special ending corner case for input packets with SAMPLE_COUNT MODULO 8 == (1 | 2) + SAMPLE1: o_tdata = {q0,i0,q1, i1, 16'b0}; + // Line one of repeating 12bit packed data pattern + SAMPLE2: o_tdata = {q0_out, i0_out, q1_out, i1_out, q0, i0[11:8]}; + // Line two of repeating 12bit packed data pattern + SAMPLE3: o_tdata = {i0_out[7:0], q1_out, i1_out, q0, i0,q1[11:4]}; + // Line three of repeating 12bit packed data pattern + SAMPLE4: o_tdata = {q1_out[3:0], i1_out, q0, i0, q1, i1}; + default : o_tdata = i_tdata; + endcase // case(state) + + + assign o_tvalid = + // We are outputing the (extra) last line of a packet + in_extra_line || + // When not in the SAMPLE1 state and there's new input data (Unless its the last line....) + (state != SAMPLE1 & i_tvalid) || + // Last line of input packet and we can finish this cycle. (Includes when state is SAMPLE1) + (i_tlast & i_tvalid & !needs_extra_line); + + assign i_tready = + // Downstream is ready and we are not currently outputing last (extra) line of packet. + (o_tready && !in_extra_line) || + // We don't create output data in SAMPLE1 unless its last line so don't need downstream ready to proceed. + ((state == SAMPLE1) && !i_tlast); + + assign o_tlast = (needs_extra_line) ? in_extra_line : i_tlast; endmodule diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v index 74aff2f08..8754d9702 100644 --- a/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v +++ b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v index 506f7b49f..57aa666b8 100644 --- a/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v +++ b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //selectable conversion chain diff --git a/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v index 681379b1a..9cff1427e 100644 --- a/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v +++ b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module chdr_32f_to_16sc diff --git a/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v index dad252d95..3ede9f578 100644 --- a/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v +++ b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v @@ -2,7 +2,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// //selectable conversion chain diff --git a/fpga/usrp3/lib/vita/new_rx_control.v b/fpga/usrp3/lib/vita/new_rx_control.v index 810fa1ce9..bf058c817 100644 --- a/fpga/usrp3/lib/vita/new_rx_control.v +++ b/fpga/usrp3/lib/vita/new_rx_control.v @@ -1,7 +1,19 @@ // // Copyright 2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // HALT brings RX to an idle state as quickly as possible if RX is running // without running the risk of leaving a packet fragment in downstream FIFO's. diff --git a/fpga/usrp3/lib/vita/new_rx_framer.v b/fpga/usrp3/lib/vita/new_rx_framer.v index 6b031a314..6594baa83 100644 --- a/fpga/usrp3/lib/vita/new_rx_framer.v +++ b/fpga/usrp3/lib/vita/new_rx_framer.v @@ -1,6 +1,10 @@ module new_rx_framer - #(parameter BASE=0) + #( + parameter BASE=0, + parameter CHIPSCOPE=0, + parameter SAMPLE_FIFO_SIZE=10 + ) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, @@ -108,7 +112,7 @@ module new_rx_framer endcase // case (instate) always @(posedge clk) - if(strobe) + if(strobe && run) begin holding <= sample; if(instate == 0) @@ -119,7 +123,7 @@ module new_rx_framer if(reset | clear) len <= 5; else - if(strobe) + if(strobe && run) if(sample_tlast) len <= 5; else @@ -146,7 +150,7 @@ module new_rx_framer wire hdr_tready; - axi_fifo #(.WIDTH(65), .SIZE(10)) datafifo + axi_fifo #(.WIDTH(65), .SIZE(SAMPLE_FIFO_SIZE)) datafifo (.clk(clk), .reset(reset), .clear(clear), .i_tdata({sample_tlast,sample_tdata}), .i_tvalid(sample_tvalid), .i_tready(sample_tready), .o_tdata({dfifo_tlast,dfifo_tdata}), .o_tvalid(dfifo_tvalid), .o_tready(dfifo_tready), @@ -209,11 +213,15 @@ module new_rx_framer .i_tdata({o_tlast_int, o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int), .o_tdata({o_tlast, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready), .space(), .occupied()); +/* -----\/----- EXCLUDED -----\/----- assign debug[3:0] = {instate, outstate}; assign debug[7:4] = {1'b0, sample_tlast, sample_tvalid, sample_tready}; assign debug[11:8] = {1'b0, 1'b0, hfifo_tvalid, hfifo_tready}; assign debug[15:12] = {1'b0, dfifo_tlast, dfifo_tvalid, dfifo_tready}; assign debug[19:16] = {1'b0, o_tlast_int, o_tvalid_int, o_tready_int}; + -----/\----- EXCLUDED -----/\----- */ + + endmodule // new_rx_framer diff --git a/fpga/usrp3/lib/vita/new_tx_control.v b/fpga/usrp3/lib/vita/new_tx_control.v index ad1300e26..4cdb54a24 100644 --- a/fpga/usrp3/lib/vita/new_tx_control.v +++ b/fpga/usrp3/lib/vita/new_tx_control.v @@ -153,7 +153,8 @@ module new_tx_control assign packet_consumed = eop & sample_tvalid & sample_tready; assign debug = { - error_code[15:0], // [28:13] + error_code[37:32], // [30:25] + error_code[11:0], // [24:13] sample_tvalid, //[12] now, // [11] early, // [10] @@ -164,7 +165,7 @@ module new_tx_control eob, // [5] send_at, // [4] odd, // [3] - state // [2:0] + state[2:0] // [2:0] }; diff --git a/fpga/usrp3/lib/vita/trigger_context_pkt.v b/fpga/usrp3/lib/vita/trigger_context_pkt.v index b67fa4313..7ce553f19 100644 --- a/fpga/usrp3/lib/vita/trigger_context_pkt.v +++ b/fpga/usrp3/lib/vita/trigger_context_pkt.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v index a71daf063..559f7f3ff 100644 --- a/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v +++ b/fpga/usrp3/lib/wishbone/axi_stream_to_wb.v @@ -1,7 +1,19 @@ // // Copyright 2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // AXI stream to/from wishbone // Input is an axi stream which wites into a BRAM. diff --git a/fpga/usrp3/lib/wishbone/settings_bus.v b/fpga/usrp3/lib/wishbone/settings_bus.v index 39f148916..3238e0ac3 100644 --- a/fpga/usrp3/lib/wishbone/settings_bus.v +++ b/fpga/usrp3/lib/wishbone/settings_bus.v @@ -1,7 +1,19 @@ // // Copyright 2011-2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock diff --git a/fpga/usrp3/lib/wishbone/settings_readback.v b/fpga/usrp3/lib/wishbone/settings_readback.v index 745571717..ce0ddd180 100644 --- a/fpga/usrp3/lib/wishbone/settings_readback.v +++ b/fpga/usrp3/lib/wishbone/settings_readback.v @@ -1,7 +1,19 @@ // // Copyright 2011-2012 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// // // Use this module in conjunction with settings_bus.v to add stateful reads diff --git a/fpga/usrp3/lib/wishbone/simple_uart.v b/fpga/usrp3/lib/wishbone/simple_uart.v index 51dc23f16..640ba884f 100644 --- a/fpga/usrp3/lib/wishbone/simple_uart.v +++ b/fpga/usrp3/lib/wishbone/simple_uart.v @@ -1,7 +1,19 @@ // // Copyright 2011 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module simple_uart diff --git a/fpga/usrp3/lib/wishbone/simple_uart_rx.v b/fpga/usrp3/lib/wishbone/simple_uart_rx.v index 7790a0a87..da4d28884 100644 --- a/fpga/usrp3/lib/wishbone/simple_uart_rx.v +++ b/fpga/usrp3/lib/wishbone/simple_uart_rx.v @@ -1,7 +1,19 @@ // // Copyright 2011-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// diff --git a/fpga/usrp3/lib/wishbone/simple_uart_tx.v b/fpga/usrp3/lib/wishbone/simple_uart_tx.v index 3eb1a1ecd..317596bba 100644 --- a/fpga/usrp3/lib/wishbone/simple_uart_tx.v +++ b/fpga/usrp3/lib/wishbone/simple_uart_tx.v @@ -1,7 +1,19 @@ // // Copyright 2011-2013 Ettus Research LLC // - +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// module simple_uart_tx |