1 files changed, 0 insertions, 71 deletions
diff --git a/fpga/usrp3/lib/xge/rtl/verilog/utils.v b/fpga/usrp3/lib/xge/rtl/verilog/utils.v
deleted file mode 100644
index 6137b3e31..000000000
--- a/fpga/usrp3/lib/xge/rtl/verilog/utils.v
+++ /dev/null
@@ -1,71 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-////  File name "utils.v"                                         ////
-////                                                              ////
-////  This file is part of the "10GE MAC" project                 ////
-////  http://www.opencores.org/cores/xge_mac/                     ////
-////                                                              ////
-////  Author(s):                                                  ////
-////      - A. Tanguay (antanguay@opencores.org)                  ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
-////                                                              ////
-//// Copyright (C) 2008 AUTHORS. All rights reserved.             ////
-////                                                              ////
-//// This source file may be used and distributed without         ////
-//// restriction provided that this copyright statement is not    ////
-//// removed from the file and that any derivative work contains  ////
-//// the original copyright notice and the associated disclaimer. ////
-////                                                              ////
-//// This source file is free software; you can redistribute it   ////
-//// and/or modify it under the terms of the GNU Lesser General   ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any   ////
-//// later version.                                               ////
-////                                                              ////
-//// This source is distributed in the hope that it will be       ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
-//// PURPOSE.  See the GNU Lesser General Public License for more ////
-//// details.                                                     ////
-////                                                              ////
-//// You should have received a copy of the GNU Lesser General    ////
-//// Public License along with this source; if not, download it   ////
-//// from http://www.opencores.org/lgpl.shtml                     ////
-////                                                              ////
-//////////////////////////////////////////////////////////////////////
- 
- 
-function [63:0] reverse_64b;
-  input [63:0]   data;
-  integer        i;
-    begin
-        for (i = 0; i < 64; i = i + 1) begin
-            reverse_64b[i] = data[63 - i];
-        end
-    end
-endfunction
- 
- 
-function [31:0] reverse_32b;
-  input [31:0]   data;
-  integer        i;
-    begin
-        for (i = 0; i < 32; i = i + 1) begin
-            reverse_32b[i] = data[31 - i];
-        end
-    end
-endfunction
- 
- 
-function [7:0] reverse_8b;
-  input [7:0]   data;
-  integer        i;
-    begin
-        for (i = 0; i < 8; i = i + 1) begin
-            reverse_8b[i] = data[7 - i];
-        end
-    end
-endfunction
- 
-