1 files changed, 70 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl
new file mode 100644
index 000000000..0f2092e6a
--- /dev/null
+++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl
@@ -0,0 +1,70 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "S_AXIS_REGISTERED" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to validate ADDRESS_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to validate ASYNC_CLK
+	return true
+}
+
+proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to validate DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to update S_AXIS_REGISTERED when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to validate S_AXIS_REGISTERED
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
+}
+
+proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.S_AXIS_REGISTERED { MODELPARAM_VALUE.S_AXIS_REGISTERED PARAM_VALUE.S_AXIS_REGISTERED } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.S_AXIS_REGISTERED}] ${MODELPARAM_VALUE.S_AXIS_REGISTERED}
+}
+