diff options
Diffstat (limited to 'fpga/usrp3/lib/vivado_ipi/util_axis_fifo')
10 files changed, 1518 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile new file mode 100644 index 000000000..d1e77a7b1 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/Makefile @@ -0,0 +1,51 @@ +#################################################################################### +#################################################################################### +## Copyright 2011(c) Analog Devices, Inc. +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS += ../common/sync_bits.v +M_DEPS += ../common/sync_gray.v +M_DEPS += ../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip.tcl +M_DEPS += address_gray.v +M_DEPS += address_gray_pipelined.v +M_DEPS += address_sync.v +M_DEPS += util_axis_fifo.v +M_DEPS += util_axis_fifo_ip.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.cache +M_FLIST += *.data +M_FLIST += *.xpr +M_FLIST += *.log +M_FLIST += component.xml +M_FLIST += *.jou +M_FLIST += xgui +M_FLIST += *.ip_user_files +M_FLIST += *.srcs +M_FLIST += *.hw +M_FLIST += *.sim +M_FLIST += .Xil + + + +.PHONY: all clean clean-all +all: util_axis_fifo.xpr + + +clean:clean-all + + +clean-all: + rm -rf $(M_FLIST) + + +util_axis_fifo.xpr: $(M_DEPS) + -rm -rf $(M_FLIST) + $(M_VIVADO) util_axis_fifo_ip.tcl >> util_axis_fifo_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v new file mode 100644 index 000000000..5c912179d --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_gray ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; + +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; + +reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next; +wire [ADDRESS_WIDTH:0] s_axis_raddr_gray; + +reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00; +wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next; +wire [ADDRESS_WIDTH:0] m_axis_waddr_gray; + +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; + +always @(*) +begin + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; +end + +assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1]; + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + s_axis_waddr_gray <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + s_axis_waddr_gray <= s_axis_waddr_gray_next; + end +end + +always @(*) +begin + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; +end + +assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1]; + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + m_axis_raddr_gray <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + m_axis_raddr_gray <= m_axis_raddr_gray_next; + end +end + +sync_bits #( + .NUM_OF_BITS(ADDRESS_WIDTH + 1) +) i_waddr_sync ( + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr_gray), + .out(m_axis_waddr_gray) +); + +sync_bits #( + .NUM_OF_BITS(ADDRESS_WIDTH + 1) +) i_raddr_sync ( + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr_gray), + .out(s_axis_raddr_gray) +); + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + end else begin + s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] || + s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] || + s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]); + s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next; + end +end + +always @(posedge m_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) + m_axis_valid <= 1'b0; + else begin + m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v new file mode 100644 index 000000000..ed7055b39 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_gray_pipelined.v @@ -0,0 +1,151 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_gray_pipelined ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output reg m_axis_valid, + output [ADDRESS_WIDTH-1:0] m_axis_raddr, + output reg [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output reg [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00; +reg [ADDRESS_WIDTH:0] _s_axis_waddr_next; +wire [ADDRESS_WIDTH:0] _s_axis_raddr; + +reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00; +reg [ADDRESS_WIDTH:0] _m_axis_raddr_next; +wire [ADDRESS_WIDTH:0] _m_axis_waddr; + +assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0]; +assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0]; + +always @(*) +begin + if (s_axis_ready && s_axis_valid) + _s_axis_waddr_next <= _s_axis_waddr + 1; + else + _s_axis_waddr_next <= _s_axis_waddr; +end + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + _s_axis_waddr <= 'h00; + end else begin + _s_axis_waddr <= _s_axis_waddr_next; + end +end + +always @(*) +begin + if (m_axis_ready && m_axis_valid) + _m_axis_raddr_next <= _m_axis_raddr + 1; + else + _m_axis_raddr_next <= _m_axis_raddr; +end + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + _m_axis_raddr <= 'h00; + end else begin + _m_axis_raddr <= _m_axis_raddr_next; + end +end + +sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) +) i_waddr_sync ( + .in_clk(s_axis_aclk), + .in_resetn(s_axis_aresetn), + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in_count(_s_axis_waddr), + .out_count(_m_axis_waddr) +); + +sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) +) i_raddr_sync ( + .in_clk(m_axis_aclk), + .in_resetn(m_axis_aresetn), + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in_count(_m_axis_raddr), + .out_count(_s_axis_raddr) +); + +always @(posedge s_axis_aclk) +begin + if (s_axis_aresetn == 1'b0) begin + s_axis_ready <= 1'b1; + s_axis_empty <= 1'b1; + s_axis_room <= 2**ADDRESS_WIDTH; + end else begin + s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] || + _s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]); + s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next; + s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH; + end +end + +always @(posedge m_axis_aclk) +begin + if (m_axis_aresetn == 1'b0) begin + m_axis_valid <= 1'b0; + m_axis_level <= 'h00; + end else begin + m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next; + m_axis_level <= _m_axis_waddr - _m_axis_raddr_next; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v new file mode 100644 index 000000000..6c94dba9c --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/address_sync.v @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module fifo_address_sync ( + input clk, + input resetn, + + input m_axis_ready, + output reg m_axis_valid, + output reg [ADDRESS_WIDTH-1:0] m_axis_raddr, + output [ADDRESS_WIDTH:0] m_axis_level, + + output reg s_axis_ready, + input s_axis_valid, + output reg s_axis_empty, + output reg [ADDRESS_WIDTH-1:0] s_axis_waddr, + output [ADDRESS_WIDTH:0] s_axis_room +); + +parameter ADDRESS_WIDTH = 4; + +reg [ADDRESS_WIDTH:0] room = 2**ADDRESS_WIDTH; +reg [ADDRESS_WIDTH:0] level = 'h00; +reg [ADDRESS_WIDTH:0] level_next; + +assign s_axis_room = room; +assign m_axis_level = level; + +wire read = m_axis_ready & m_axis_valid; +wire write = s_axis_ready & s_axis_valid; + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + s_axis_waddr <= 'h00; + m_axis_raddr <= 'h00; + end else begin + if (write) + s_axis_waddr <= s_axis_waddr + 1'b1; + if (read) + m_axis_raddr <= m_axis_raddr + 1'b1; + end +end + +always @(*) +begin + if (read & ~write) + level_next <= level - 1'b1; + else if (~read & write) + level_next <= level + 1'b1; + else + level_next <= level; +end + +always @(posedge clk) +begin + if (resetn == 1'b0) begin + m_axis_valid <= 1'b0; + s_axis_ready <= 1'b0; + level <= 'h00; + room <= 2**ADDRESS_WIDTH; + s_axis_empty <= 'h00; + end else begin + level <= level_next; + room <= 2**ADDRESS_WIDTH - level_next; + m_axis_valid <= level_next != 0; + s_axis_ready <= level_next != 2**ADDRESS_WIDTH; + s_axis_empty <= level_next == 0; + end +end + +endmodule + diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml new file mode 100644 index 000000000..44d9a2af4 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/component.xml @@ -0,0 +1,542 @@ +<?xml version="1.0" encoding="UTF-8"?> +<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"> + <spirit:vendor>analog.com</spirit:vendor> + <spirit:library>user</spirit:library> + <spirit:name>util_axis_fifo</spirit:name> + <spirit:version>1.0</spirit:version> + <spirit:busInterfaces> + <spirit:busInterface> + <spirit:name>S_AXIS</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_ready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>s_axis_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>M_AXIS</spirit:name> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/> + <spirit:master/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TVALID</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_valid</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TREADY</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_ready</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>TDATA</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_data</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>M_AXIS_signal_clock</spirit:name> + <spirit:displayName>M_AXIS_signal_clock</spirit:displayName> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_aclk</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>ASSOCIATED_BUSIF</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_BUSIF">M_AXIS</spirit:value> + </spirit:parameter> + <spirit:parameter> + <spirit:name>ASSOCIATED_RESET</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_CLOCK.ASSOCIATED_RESET">m_axis_aresetn</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>M_AXIS_signal_reset</spirit:name> + <spirit:displayName>M_AXIS_signal_reset</spirit:displayName> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>RST</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + <spirit:name>m_axis_aresetn</spirit:name> + </spirit:physicalPort> + </spirit:portMap> + </spirit:portMaps> + <spirit:parameters> + <spirit:parameter> + <spirit:name>POLARITY</spirit:name> + <spirit:value spirit:id="BUSIFPARAM_VALUE.M_AXIS_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value> + </spirit:parameter> + </spirit:parameters> + </spirit:busInterface> + <spirit:busInterface> + <spirit:name>S_AXIS_signal_clock</spirit:name> + <spirit:displayName>S_AXIS_signal_clock</spirit:displayName> + <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/> + <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/> + <spirit:slave/> + <spirit:portMaps> + <spirit:portMap> + <spirit:logicalPort> + <spirit:name>CLK</spirit:name> + </spirit:logicalPort> + <spirit:physicalPort> + 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a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v new file mode 100644 index 000000000..2530f047b --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_bits.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ +module sync_bits +( + input [NUM_OF_BITS-1:0] in, + input out_resetn, + input out_clk, + output [NUM_OF_BITS-1:0] out +); + +// Number of bits to synchronize +parameter NUM_OF_BITS = 1; +// Whether input and output clocks are asynchronous, if 0 the synchronizer will +// be bypassed and the output signal equals the input signal. +parameter ASYNC_CLK = 1; + +reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; +reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; + +always @(posedge out_clk) +begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'b0; + cdc_sync_stage2 <= 'b0; + end else begin + cdc_sync_stage1 <= in; + cdc_sync_stage2 <= cdc_sync_stage1; + end +end + +assign out = ASYNC_CLK ? cdc_sync_stage2 : in; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v new file mode 100644 index 000000000..2b67e1266 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/sync_gray.v @@ -0,0 +1,111 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing a counter from one clock domain to another + * using gray code. To work correctly the counter must not change its value by + * more than one in one clock cycle in the source domain. I.e. the value may + * change by either -1, 0 or +1. + */ +module sync_gray ( + input in_clk, + input in_resetn, + input [DATA_WIDTH-1:0] in_count, + input out_resetn, + input out_clk, + output [DATA_WIDTH-1:0] out_count +); + +// Bit-width of the counter +parameter DATA_WIDTH = 1; +// Whether the input and output clock are asynchronous, if set to 0 the +// synchronizer will be bypassed and out_count will be in_count. +parameter ASYNC_CLK = 1; + +reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0; +reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0; +reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0; +reg [DATA_WIDTH-1:0] out_count_m = 'h0; + +function [DATA_WIDTH-1:0] g2b; + input [DATA_WIDTH-1:0] g; + reg [DATA_WIDTH-1:0] b; + integer i; + begin + b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end +endfunction + +function [DATA_WIDTH-1:0] b2g; + input [DATA_WIDTH-1:0] b; + reg [DATA_WIDTH-1:0] g; + integer i; + begin + g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end +endfunction + +always @(posedge in_clk) begin + if (in_resetn == 1'b0) begin + cdc_sync_stage0 <= 'h00; + end else begin + cdc_sync_stage0 <= b2g(in_count); + end +end + +always @(posedge out_clk) begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'h00; + cdc_sync_stage2 <= 'h00; + out_count_m <= 'h00; + end else begin + cdc_sync_stage1 <= cdc_sync_stage0; + cdc_sync_stage2 <= cdc_sync_stage1; + out_count_m <= g2b(cdc_sync_stage2); + end +end + +assign out_count = ASYNC_CLK ? out_count_m : in_count; + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v new file mode 100644 index 000000000..f2661daa1 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo.v @@ -0,0 +1,215 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// Author: Lars-Peter Clausen <lars@metafoo.de> +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// Source: git://github.com/analogdevicesinc/hdl.git +// Commit hash: 04843795d8d6a496c00ee91b437d57924bc1cbf1 + +module util_axis_fifo ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DATA_WIDTH-1:0] m_axis_data, + output [ADDRESS_WIDTH:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [DATA_WIDTH-1:0] s_axis_data, + output s_axis_empty, + output [ADDRESS_WIDTH:0] s_axis_room +); + +parameter DATA_WIDTH = 64; +parameter ASYNC_CLK = 1; +parameter ADDRESS_WIDTH = 4; +parameter S_AXIS_REGISTERED = 1; + +generate if (ADDRESS_WIDTH == 0) begin + +reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; +reg s_axis_waddr = 1'b0; +reg m_axis_raddr = 1'b0; + +wire m_axis_waddr; +wire s_axis_raddr; + +sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) +) i_waddr_sync ( + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in(s_axis_waddr), + .out(m_axis_waddr) +); + +sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) +) i_raddr_sync ( + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in(m_axis_raddr), + .out(s_axis_raddr) +); + +assign m_axis_valid = m_axis_raddr != m_axis_waddr; +assign m_axis_level = m_axis_valid; +assign s_axis_ready = s_axis_raddr == s_axis_waddr; +assign s_axis_empty = s_axis_ready; +assign s_axis_room = s_axis_ready; + +always @(posedge s_axis_aclk) begin + if (s_axis_ready) + cdc_sync_fifo_ram <= s_axis_data; +end + +always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + s_axis_waddr <= 1'b0; + end else begin + if (s_axis_ready & s_axis_valid) begin + s_axis_waddr <= s_axis_waddr + 1'b1; + end + end +end + +always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + m_axis_raddr <= 1'b0; + end else begin + if (m_axis_valid & m_axis_ready) + m_axis_raddr <= m_axis_raddr + 1'b1; + end +end + +assign m_axis_data = cdc_sync_fifo_ram; + +end else begin + +reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1]; + +wire [ADDRESS_WIDTH-1:0] s_axis_waddr; +wire [ADDRESS_WIDTH-1:0] m_axis_raddr; +wire _m_axis_ready; +wire _m_axis_valid; + +if (ASYNC_CLK == 1) begin + +fifo_address_gray_pipelined #( + .ADDRESS_WIDTH(ADDRESS_WIDTH) +) i_address_gray ( + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), + + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) +); + +end else begin + +fifo_address_sync #( + .ADDRESS_WIDTH(ADDRESS_WIDTH) +) i_address_sync ( + .clk(m_axis_aclk), + .resetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), + + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_empty(s_axis_empty), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room) +); + +end + +always @(posedge s_axis_aclk) begin + if (s_axis_ready) + ram[s_axis_waddr] <= s_axis_data; +end + +if (S_AXIS_REGISTERED == 1) begin + +reg [DATA_WIDTH-1:0] data; +reg valid; + +always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + valid <= 1'b0; + end else begin + if (_m_axis_valid) + valid <= 1'b1; + else if (m_axis_ready) + valid <= 1'b0; + end +end + +always @(posedge m_axis_aclk) begin + if (~valid || m_axis_ready) + data <= ram[m_axis_raddr]; +end + +assign _m_axis_ready = ~valid || m_axis_ready; +assign m_axis_data = data; +assign m_axis_valid = valid; + +end else begin + +assign _m_axis_ready = m_axis_ready; +assign m_axis_valid = _m_axis_valid; +assign m_axis_data = ram[m_axis_raddr]; + +end + +end endgenerate + +endmodule diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl new file mode 100644 index 000000000..014409288 --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/util_axis_fifo_ip.tcl @@ -0,0 +1,38 @@ + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_axis_fifo +adi_ip_files util_axis_fifo [list \ + "$ad_hdl_dir/library/common/sync_bits.v" \ + "$ad_hdl_dir/library/common/sync_gray.v" \ + "address_gray.v" \ + "address_gray_pipelined.v" \ + "address_sync.v" \ + "util_axis_fifo.v" \ +] + +adi_ip_properties_lite util_axis_fifo + +adi_add_bus "S_AXIS" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + } + +adi_add_bus_clock "m_axis_aclk" "M_AXIS" "m_axis_aresetn" +adi_add_bus_clock "s_axis_aclk" "S_AXIS" "m_axis_aresetn" + +ipx::save_core [ipx::current_core] diff --git a/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl new file mode 100644 index 000000000..0f2092e6a --- /dev/null +++ b/fpga/usrp3/lib/vivado_ipi/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_AXIS_REGISTERED" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to update S_AXIS_REGISTERED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to validate S_AXIS_REGISTERED + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.S_AXIS_REGISTERED { MODELPARAM_VALUE.S_AXIS_REGISTERED PARAM_VALUE.S_AXIS_REGISTERED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXIS_REGISTERED}] ${MODELPARAM_VALUE.S_AXIS_REGISTERED} +} + |