diff options
Diffstat (limited to 'fpga/usrp3/lib/sim')
| -rw-r--r-- | fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile index f0cdb3704..eb764749f 100644 --- a/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile +++ b/fpga/usrp3/lib/sim/dsp/mult_add_clip/Makefile @@ -25,13 +25,14 @@ $(DSP_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = mult_add_clip_tb +# Define toplevel module +SIM_TOP = mult_add_clip_tb glbl # Add test bench, user design under test, and # additional user created files SIM_SRCS = $(abspath \ mult_add_clip_tb.sv \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ ) # MODELSIM_USER_DO = $(abspath wave.do) |