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-rw-r--r--fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v7
1 files changed, 0 insertions, 7 deletions
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
index 50a4b7615..2f7ee11d8 100644
--- a/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
+++ b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v
@@ -231,7 +231,6 @@ module axis_data_to_chdr #(
wire in_pyld_tlast;
wire in_pyld_tvalid;
wire in_pyld_tready;
- wire width_conv_tready;
wire [CHDR_W-1:0] out_pyld_tdata;
wire out_pyld_tlast;
@@ -368,12 +367,6 @@ module axis_data_to_chdr #(
endgenerate
-
-
-
-
-
-
// This state machine prevents data from transferring when the pkt_info_fifo
// is stalled. This ensures that we don't overflow the pkt_info_fifo.
always @(posedge axis_chdr_clk) begin