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| author | Wade Fife <wade.fife@ettus.com> | 2020-04-06 16:19:50 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-08-04 15:40:08 -0500 |
| commit | 6d92a1828121ca4b57d496bbf522820f961244b9 (patch) | |
| tree | f0659ab6d1a6e1f8801db356e2237388d90724f2 /fpga/usrp3/lib/rfnoc/core | |
| parent | 24f8bb39fd2769ff93d11b21152a834500152de4 (diff) | |
| download | uhd-6d92a1828121ca4b57d496bbf522820f961244b9.tar.gz uhd-6d92a1828121ca4b57d496bbf522820f961244b9.tar.bz2 uhd-6d92a1828121ca4b57d496bbf522820f961244b9.zip | |
fpga: rfnoc: Add RFNoC Replay block
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/core')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v index 50a4b7615..2f7ee11d8 100644 --- a/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v +++ b/fpga/usrp3/lib/rfnoc/core/axis_data_to_chdr.v @@ -231,7 +231,6 @@ module axis_data_to_chdr #( wire in_pyld_tlast; wire in_pyld_tvalid; wire in_pyld_tready; - wire width_conv_tready; wire [CHDR_W-1:0] out_pyld_tdata; wire out_pyld_tlast; @@ -368,12 +367,6 @@ module axis_data_to_chdr #( endgenerate - - - - - - // This state machine prevents data from transferring when the pkt_info_fifo // is stalled. This ensures that we don't overflow the pkt_info_fifo. always @(posedge axis_chdr_clk) begin |