diff options
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile | 52 |
1 files changed, 19 insertions, 33 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile index d574c9a01..b63685ef7 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # @@ -7,57 +7,43 @@ #------------------------------------------------- # Top-of-Makefile #------------------------------------------------- -# Define BASE_DIR to point to the "top" dir -BASE_DIR = $(abspath ../../../../top) -# Include viv_sim_preamble after defining BASE_DIR +# Define BASE_DIR to point to the "top" dir. Note: +# UHD_FPGA_DIR must be passed into this Makefile. +BASE_DIR = ../../../../top +# Include viv_sim_preample after defining BASE_DIR include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak #------------------------------------------------- -# IP Specific -#------------------------------------------------- -# If simulation contains IP, define the IP_DIR and point -# it to the base level IP directory -LIB_IP_DIR = $(BASE_DIR)/../lib/ip - -# Include makefiles and sources for all IP components -# *after* defining the LIB_IP_DIR -#include $(LIB_IP_DIR)/axi_fft/Makefile.inc -#include $(LIB_IP_DIR)/complex_to_magphase/Makefile.inc -include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc -include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc -include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs - -DESIGN_SRCS += $(abspath \ -$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \ -$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ -$(COREGEN_DSP_SRCS) \ -) - -#------------------------------------------------- # Design Specific #------------------------------------------------- -# Include makefiles and sources for the DUT and its dependencies +# Include makefiles and sources for the DUT and its +# dependencies. include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include $(LIB_IP_DIR)/complex_multiplier_dds/Makefile.inc +include $(LIB_IP_DIR)/dds_sin_cos_lut_only/Makefile.inc +include $(BASE_DIR)/x300/coregen_dsp/Makefile.srcs include Makefile.srcs DESIGN_SRCS += $(abspath \ $(RFNOC_CORE_SRCS) \ $(RFNOC_UTIL_SRCS) \ +$(LIB_IP_COMPLEX_MULTIPLIER_DDS_SRCS) \ +$(LIB_IP_DDS_SIN_COS_LUT_ONLY_SRCS) \ +$(COREGEN_DSP_SRCS) \ $(RFNOC_BLOCK_DDC_SRCS) \ ) #------------------------------------------------- # Testbench Specific #------------------------------------------------- -# Define only one toplevel module -SIM_TOP = rfnoc_block_ddc_tb - -# Add test bench, user design under test, and -# additional user created files +MODELSIM_LIBS += unimacro_ver +SIM_TOP = rfnoc_block_ddc_tb glbl SIM_SRCS = \ -$(COREGEN_DSP_SRCS) \ -$(abspath rfnoc_block_ddc_tb.sv) +$(abspath $(IP_BUILD_DIR)/dds_sin_cos_lut_only/sim/dds_sin_cos_lut_only.vhd) \ +$(abspath $(IP_BUILD_DIR)/complex_multiplier_dds/sim/complex_multiplier_dds.vhd) \ +$(abspath rfnoc_block_ddc_tb.sv) \ +$(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- # Bottom-of-Makefile |