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-rw-r--r--firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx30
-rw-r--r--firmware/fx3/gpif2_designer/b200_v2.cydsn/cyfxgpif2config.h174
-rw-r--r--firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml140
-rw-r--r--firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml49
-rw-r--r--firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2view.xml183
5 files changed, 576 insertions, 0 deletions
diff --git a/firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx b/firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx
new file mode 100644
index 000000000..3e6eb0719
--- /dev/null
+++ b/firmware/fx3/gpif2_designer/b200_v2.cydsn/b200_v2.cyfx
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="us-ascii"?>
+<CyXmlSerializer>
+<!--This file is machine generated and read. It is not intended to be edited by hand.-->
+<!--Due to this, there is no schema for this file.-->
+<CyGuid_7d237aff-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtGpif2exe" version="2">
+<CyGuid_7d237b00-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtProject" version="1">
+<ProjectDocs>
+<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2model.xml" persistent="./projectfiles/gpif2model.xml" target="7d237b02-d944-11da-aaba-00164119d63b">
+<Hidden v="False" />
+</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
+<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2view.xml" persistent="./projectfiles/gpif2view.xml" target="7d237b01-d944-11da-aaba-00164119d63b">
+<Hidden v="False" />
+</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
+<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="gpif2timingsimulation.xml" persistent="./projectfiles/gpif2timingsimulation.xml" target="3ad448c6-d155-4f76-a7fb-e760cd8e6feb">
+<Hidden v="False" />
+</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
+</ProjectDocs>
+<OutputDocs>
+<CyGuid_7d237b03-d944-11da-aaba-00164119d63b type_name="CyGpif2Designer.Common.PrjMgmt.Model.CyPrjMgmtItem" name="cyfxgpif2config.h" persistent="C:\Users\bhilburn\Documents\GPIF II Designer\b200_v2.cydsn\cyfxgpif2config.h" target="7d237afd-d944-11da-aaba-00164119d63b">
+<Hidden v="False" />
+</CyGuid_7d237b03-d944-11da-aaba-00164119d63b>
+</OutputDocs>
+</CyGuid_7d237b00-d944-11da-aaba-00164119d63b>
+<Settings>
+<Setting name="GPIF2_OutputName" value="cyfxgpif2config" />
+<Setting name="GPIF2_OutputLocation" value="C:\Users\bhilburn\Documents\GPIF II Designer\b200_v2.cydsn" />
+<Setting name="GPIF2_Template" value="C:\Program Files\Cypress\GPIFII Designer\inputs\outputtemplates\cygpif2cheadertemplate.tpl" />
+</Settings>
+</CyGuid_7d237aff-d944-11da-aaba-00164119d63b>
+</CyXmlSerializer> \ No newline at end of file
diff --git a/firmware/fx3/gpif2_designer/b200_v2.cydsn/cyfxgpif2config.h b/firmware/fx3/gpif2_designer/b200_v2.cydsn/cyfxgpif2config.h
new file mode 100644
index 000000000..d16cdf038
--- /dev/null
+++ b/firmware/fx3/gpif2_designer/b200_v2.cydsn/cyfxgpif2config.h
@@ -0,0 +1,174 @@
+/*
+ * Project Name: b200_v2.cyfx
+ * Time : 10/23/2013 12:03:48
+ * Device Type: FX3
+ * Project Type: GPIF2
+ *
+ *
+ *
+ *
+ * This is a generated file and should not be modified
+ * This file need to be included only once in the firmware
+ * This file is generated by Gpif2 designer tool version - 1.0.715.0
+ *
+ */
+
+#ifndef _INCLUDED_CYFXGPIF2CONFIG_
+#define _INCLUDED_CYFXGPIF2CONFIG_
+#include "cyu3types.h"
+#include "cyu3gpif.h"
+
+/* Summary
+ Number of states in the state machine
+ */
+#define CY_NUMBER_OF_STATES 6
+
+/* Summary
+ Mapping of user defined state names to state indices
+ */
+#define RESET 0
+#define IDLE 1
+#define READ 2
+#define WRITE 3
+#define SHORT_PKT 4
+#define ZLP 5
+
+
+/* Summary
+ Initial value of early outputs from the state machine.
+ */
+#define ALPHA_RESET 0x8
+
+
+/* Summary
+ Transition function values used in the state machine.
+ */
+uint16_t CyFxGpifTransition[] = {
+ 0x0000, 0x8080, 0x2222, 0x5555, 0x7F7F, 0x1F1F, 0x8888
+};
+
+/* Summary
+ Table containing the transition information for various states.
+ This table has to be stored in the WAVEFORM Registers.
+ This array consists of non-replicated waveform descriptors and acts as a
+ waveform table.
+ */
+CyU3PGpifWaveData CyFxGpifWavedata[] = {
+ {{0x1E086001,0x000100C4,0x80000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x4E080302,0x00000200,0x80000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x1E086001,0x000100C4,0x80000000},{0x4E040704,0x20000200,0xC0100000}},
+ {{0x00000000,0x00000000,0x00000000},{0x00000000,0x00000000,0x00000000}},
+ {{0x00000000,0x00000000,0x00000000},{0x3E738705,0x00000200,0xC0100000}},
+ {{0x00000000,0x00000000,0x00000000},{0x5E002703,0x2001020C,0x80000000}},
+ {{0x00000000,0x00000000,0x00000000},{0x4E040704,0x20000200,0xC0100000}}
+};
+
+/* Summary
+ Table that maps state indices to the descriptor table indices.
+ */
+uint8_t CyFxGpifWavedataPosition[] = {
+ 0,1,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,4,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,5,0,2,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,
+ 0,6,0,2,0,0
+};
+
+/* Summary
+ GPIF II configuration register values.
+ */
+uint32_t CyFxGpifRegValue[] = {
+ 0x80000380, /* CY_U3P_PIB_GPIF_CONFIG */
+ 0x000010AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
+ 0x01070002, /* CY_U3P_PIB_GPIF_BUS_CONFIG2 */
+ 0x00000044, /* CY_U3P_PIB_GPIF_AD_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_STATUS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INTR */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INTR_MASK */
+ 0x00000082, /* CY_U3P_PIB_GPIF_SERIAL_IN_CONFIG */
+ 0x00000782, /* CY_U3P_PIB_GPIF_SERIAL_OUT_CONFIG */
+ 0x00000500, /* CY_U3P_PIB_GPIF_CTRL_BUS_DIRECTION */
+ 0x0000FFCF, /* CY_U3P_PIB_GPIF_CTRL_BUS_DEFAULT */
+ 0x000000BF, /* CY_U3P_PIB_GPIF_CTRL_BUS_POLARITY */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_TOGGLE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000018, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000019, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_BUS_SELECT */
+ 0x00000006, /* CY_U3P_PIB_GPIF_CTRL_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_CTRL_COUNT_LIMIT */
+ 0x0000010A, /* CY_U3P_PIB_GPIF_ADDR_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_ADDR_COUNT_LIMIT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_STATE_COUNT_CONFIG */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_STATE_COUNT_LIMIT */
+ 0x0000010A, /* CY_U3P_PIB_GPIF_DATA_COUNT_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COUNT_RESET */
+ 0x0000FFFF, /* CY_U3P_PIB_GPIF_DATA_COUNT_LIMIT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CTRL_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_VALUE */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ADDR_COMP_MASK */
+ 0x00000000, /* CY_U3P_PIB_GPIF_DATA_CTRL */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_DATA */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_INGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x00000000, /* CY_U3P_PIB_GPIF_EGRESS_ADDRESS */
+ 0x80010400, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010401, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010402, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x80010403, /* CY_U3P_PIB_GPIF_THREAD_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_LAMBDA_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_ALPHA_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_BETA_STAT */
+ 0x00080000, /* CY_U3P_PIB_GPIF_WAVEFORM_CTRL_STAT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH */
+ 0x00000000, /* CY_U3P_PIB_GPIF_WAVEFORM_SWITCH_TIMEOUT */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_CONFIG */
+ 0x00000000, /* CY_U3P_PIB_GPIF_CRC_DATA */
+ 0xFFFFFFF1 /* CY_U3P_PIB_GPIF_BETA_DEASSERT */
+};
+
+/* Summary
+ This structure holds all the configuration inputs for the GPIF II.
+ */
+const CyU3PGpifConfig_t CyFxGpifConfig = {
+ (uint16_t)(sizeof(CyFxGpifWavedataPosition)/sizeof(uint8_t)),
+ CyFxGpifWavedata,
+ CyFxGpifWavedataPosition,
+ (uint16_t)(sizeof(CyFxGpifTransition)/sizeof(uint16_t)),
+ CyFxGpifTransition,
+ (uint16_t)(sizeof(CyFxGpifRegValue)/sizeof(uint32_t)),
+ CyFxGpifRegValue
+};
+
+#endif /* _INCLUDED_CYFXGPIF2CONFIG_ */
diff --git a/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml
new file mode 100644
index 000000000..477bad9e7
--- /dev/null
+++ b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2model.xml
@@ -0,0 +1,140 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GPIFIIModel version="3">
+ <InterfaceDefination>
+ <InterfaceSetting>
+ <I2SEnabled>False</I2SEnabled>
+ <I2CEnabled>False</I2CEnabled>
+ <SPIEnabled>False</SPIEnabled>
+ <I2SEnabled>False</I2SEnabled>
+ <ADMuxedEnabled>False</ADMuxedEnabled>
+ <InterfaceType>Slave</InterfaceType>
+ <CommunicationType>Synchronous</CommunicationType>
+ <ClockSource>External</ClockSource>
+ <ClockEdge>Positive</ClockEdge>
+ <Endianness>LittleEndian</Endianness>
+ <DataBusWidth>Bit32</DataBusWidth>
+ <AddressBuswidth>2</AddressBuswidth>
+ </InterfaceSetting>
+ </InterfaceDefination>
+ <Signals>
+ <Signal ElementId="INPUT0" SignalType="Input" SpecialFunction="OE">
+ <DisplayName>SLOE</DisplayName>
+ <GPIOPinNumber>GPIO_19</GPIOPinNumber>
+ <Polarity>ActiveLow</Polarity>
+ </Signal>
+ <Signal ElementId="INPUT1" SignalType="Input" SpecialFunction="None">
+ <DisplayName>SLCS</DisplayName>
+ <GPIOPinNumber>GPIO_17</GPIOPinNumber>
+ <Polarity>ActiveLow</Polarity>
+ </Signal>
+ <Signal ElementId="INPUT2" SignalType="Input" SpecialFunction="None">
+ <DisplayName>SLWR</DisplayName>
+ <GPIOPinNumber>GPIO_18</GPIOPinNumber>
+ <Polarity>ActiveLow</Polarity>
+ </Signal>
+ <Signal ElementId="INPUT3" SignalType="Input" SpecialFunction="None">
+ <DisplayName>SLRD</DisplayName>
+ <GPIOPinNumber>GPIO_20</GPIOPinNumber>
+ <Polarity>ActiveLow</Polarity>
+ </Signal>
+ <Signal ElementId="INPUT4" SignalType="Input" SpecialFunction="None">
+ <DisplayName>PKEND</DisplayName>
+ <GPIOPinNumber>GPIO_24</GPIOPinNumber>
+ <Polarity>ActiveLow</Polarity>
+ </Signal>
+ <Signal ElementId="FLAG0" SignalType="Flags" SpecialFunction="None">
+ <DisplayName>FLAG0</DisplayName>
+ <GPIOPinNumber>GPIO_21</GPIOPinNumber>
+ <IntialValue>Low</IntialValue>
+ <Polarity>ActiveLow</Polarity>
+ <Flags>Current_Thread_DMA_Ready</Flags>
+ </Signal>
+ <Signal ElementId="FLAG1" SignalType="Flags" SpecialFunction="None">
+ <DisplayName>FLAG1</DisplayName>
+ <GPIOPinNumber>GPIO_22</GPIOPinNumber>
+ <IntialValue>Low</IntialValue>
+ <Polarity>ActiveLow</Polarity>
+ <Flags>Current_Thread_DMA_WaterMark</Flags>
+ </Signal>
+ </Signals>
+ <StateMachine>
+ <AddressCounter />
+ <DataCounter />
+ <ControlCounter />
+ <AddressComparator />
+ <DataComparator />
+ <ControlComparator />
+ <DRQ />
+ <AddrData />
+ <State ElementId="STARTSTATE1" StateType="StartState">
+ <DisplayName>RESET</DisplayName>
+ <RepeatUntillNextTransition>True</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ </State>
+ <State ElementId="STATE1" StateType="NormalState">
+ <DisplayName>IDLE</DisplayName>
+ <RepeatUntillNextTransition>True</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ <Action ElementId="IN_ADDR0" ActionType="IN_ADDR">
+ <SampleAddressType>ThreadSelection</SampleAddressType>
+ <A7Override>DMAAccessAndRegisterAccess</A7Override>
+ </Action>
+ </State>
+ <State ElementId="STATE2" StateType="NormalState">
+ <DisplayName>READ</DisplayName>
+ <RepeatUntillNextTransition>True</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ <Action ElementId="DR_DATA0" ActionType="DR_DATA">
+ <IsDataCounterConnected>False</IsDataCounterConnected>
+ <DataSourceSink>Socket</DataSourceSink>
+ <ThreadNumber>Thread0</ThreadNumber>
+ <SyncBurstMode>Enable</SyncBurstMode>
+ <DriveNewData>DriveNewData</DriveNewData>
+ <UpdateSource>True</UpdateSource>
+ </Action>
+ </State>
+ <State ElementId="STATE3" StateType="NormalState">
+ <DisplayName>WRITE</DisplayName>
+ <RepeatUntillNextTransition>True</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ <Action ElementId="IN_DATA0" ActionType="IN_DATA">
+ <DataSourceSink>Socket</DataSourceSink>
+ <ThreadNumber>Thread0</ThreadNumber>
+ <SampleData>True</SampleData>
+ <WriteDataIntoDataSink>True</WriteDataIntoDataSink>
+ </Action>
+ </State>
+ <State ElementId="STATE4" StateType="NormalState">
+ <DisplayName>SHORT_PKT</DisplayName>
+ <RepeatUntillNextTransition>False</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ <Action ElementId="COMMIT0" ActionType="COMMIT">
+ <ThreadNumber>Thread0</ThreadNumber>
+ </Action>
+ <Action ElementId="IN_DATA0" ActionType="IN_DATA">
+ <DataSourceSink>Socket</DataSourceSink>
+ <ThreadNumber>Thread0</ThreadNumber>
+ <SampleData>True</SampleData>
+ <WriteDataIntoDataSink>True</WriteDataIntoDataSink>
+ </Action>
+ </State>
+ <State ElementId="STATE5" StateType="NormalState">
+ <DisplayName>ZLP</DisplayName>
+ <RepeatUntillNextTransition>False</RepeatUntillNextTransition>
+ <RepeatCount>0</RepeatCount>
+ <Action ElementId="COMMIT0" ActionType="COMMIT">
+ <ThreadNumber>Thread0</ThreadNumber>
+ </Action>
+ </State>
+ <Transition ElementId="TRANSITION1" SourceState="STARTSTATE1" DestinationState="STATE1" Equation="LOGIC_ONE" />
+ <Transition ElementId="TRANSITION2" SourceState="STATE1" DestinationState="STATE2" Equation="SLWR&amp;!SLCS&amp;PKEND&amp;!SLRD&amp;!SLOE" />
+ <Transition ElementId="TRANSITION3" SourceState="STATE1" DestinationState="STATE3" Equation="!SLWR&amp;!SLCS&amp;PKEND&amp;SLRD" />
+ <Transition ElementId="TRANSITION4" SourceState="STATE1" DestinationState="STATE4" Equation="!SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD" />
+ <Transition ElementId="TRANSITION5" SourceState="STATE1" DestinationState="STATE5" Equation="SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD" />
+ <Transition ElementId="TRANSITION6" SourceState="STATE5" DestinationState="STATE1" Equation="PKEND" />
+ <Transition ElementId="TRANSITION7" SourceState="STATE2" DestinationState="STATE1" Equation="SLRD|SLCS|SLOE" />
+ <Transition ElementId="TRANSITION8" SourceState="STATE3" DestinationState="STATE1" Equation="(PKEND&amp;SLWR)|SLCS" />
+ <Transition ElementId="TRANSITION9" SourceState="STATE3" DestinationState="STATE4" Equation="!SLWR&amp;!PKEND" />
+ <Transition ElementId="TRANSITION10" SourceState="STATE4" DestinationState="STATE1" Equation="PKEND|SLCS|SLWR" />
+ </StateMachine>
+</GPIFIIModel> \ No newline at end of file
diff --git a/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml
new file mode 100644
index 000000000..e6b10027b
--- /dev/null
+++ b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2timingsimulation.xml
@@ -0,0 +1,49 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GPIFIITimingSimulation version="1">
+ <Clock>100</Clock>
+ <BufferSize>512</BufferSize>
+ <WaterMark>0</WaterMark>
+ <Scenario Name="Read" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE2" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+ <Scenario Name="Write" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+ <Scenario Name="BurstRead" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE2" WaitNumber="0" />
+ <State StateId="STATE2" WaitNumber="0" />
+ <State StateId="STATE2" WaitNumber="0" />
+ <State StateId="STATE2" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+ <Scenario Name="BurstWrite" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE3" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+ <Scenario Name="ShortPkt" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE4" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+ <Scenario Name="ZLP" CurrentThread="Thread0">
+ <State StateId="STARTSTATE1" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ <State StateId="STATE5" WaitNumber="0" />
+ <State StateId="STATE1" WaitNumber="0" />
+ </Scenario>
+</GPIFIITimingSimulation> \ No newline at end of file
diff --git a/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2view.xml b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2view.xml
new file mode 100644
index 000000000..730be04ab
--- /dev/null
+++ b/firmware/fx3/gpif2_designer/b200_v2.cydsn/projectfiles/gpif2view.xml
@@ -0,0 +1,183 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Root version="4">
+ <CyStates>
+ <CyNormalState>
+ <Left>363</Left>
+ <Top>96.4466666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STATE1</Name>
+ <DisplayName>IDLE</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyNormalState>
+ <CyNormalState>
+ <Left>237</Left>
+ <Top>390.446666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STATE2</Name>
+ <DisplayName>READ</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyNormalState>
+ <CyNormalState>
+ <Left>551</Left>
+ <Top>379.446666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STATE3</Name>
+ <DisplayName>WRITE</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyNormalState>
+ <CyNormalState>
+ <Left>773</Left>
+ <Top>233.446666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STATE4</Name>
+ <DisplayName>SHORT_PKT</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyNormalState>
+ <CyNormalState>
+ <Left>11</Left>
+ <Top>196.446666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STATE5</Name>
+ <DisplayName>ZLP</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyNormalState>
+ <CyStartState>
+ <Left>29</Left>
+ <Top>18.4466666666667</Top>
+ <Width>83</Width>
+ <Height>70</Height>
+ <Name>STARTSTATE1</Name>
+ <DisplayName>RESET</DisplayName>
+ <zIndex>1</zIndex>
+ <IsGroup>False</IsGroup>
+ <ParentID>00000000-0000-0000-0000-000000000000</ParentID>
+ </CyStartState>
+ </CyStates>
+ <CyTransitions>
+ <CyTransition>
+ <Name>TRANSITION1</Name>
+ <TransitionEquation>LOGIC_ONE</TransitionEquation>
+ <SourceName>STARTSTATE1</SourceName>
+ <SinkName>STATE1</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION2</Name>
+ <TransitionEquation>SLWR&amp;!SLCS&amp;PKEND&amp;!SLRD&amp;!SLOE</TransitionEquation>
+ <SourceName>STATE1</SourceName>
+ <SinkName>STATE2</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION3</Name>
+ <TransitionEquation>!SLWR&amp;!SLCS&amp;PKEND&amp;SLRD</TransitionEquation>
+ <SourceName>STATE1</SourceName>
+ <SinkName>STATE3</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION4</Name>
+ <TransitionEquation>!SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD</TransitionEquation>
+ <SourceName>STATE1</SourceName>
+ <SinkName>STATE4</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION5</Name>
+ <TransitionEquation>SLWR&amp;!SLCS&amp;!PKEND&amp;SLRD</TransitionEquation>
+ <SourceName>STATE1</SourceName>
+ <SinkName>STATE5</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION6</Name>
+ <TransitionEquation>PKEND</TransitionEquation>
+ <SourceName>STATE5</SourceName>
+ <SinkName>STATE1</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION7</Name>
+ <TransitionEquation>SLRD|SLCS|SLOE</TransitionEquation>
+ <SourceName>STATE2</SourceName>
+ <SinkName>STATE1</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION8</Name>
+ <TransitionEquation>(PKEND&amp;SLWR)|SLCS</TransitionEquation>
+ <SourceName>STATE3</SourceName>
+ <SinkName>STATE1</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION9</Name>
+ <TransitionEquation>!SLWR&amp;!PKEND</TransitionEquation>
+ <SourceName>STATE3</SourceName>
+ <SinkName>STATE4</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ <CyTransition>
+ <Name>TRANSITION10</Name>
+ <TransitionEquation>PKEND|SLCS|SLWR</TransitionEquation>
+ <SourceName>STATE4</SourceName>
+ <SinkName>STATE1</SinkName>
+ <SourceConnectorName>Connector</SourceConnectorName>
+ <SinkConnectorName>Connector</SinkConnectorName>
+ <SourceArrowSymbol>None</SourceArrowSymbol>
+ <SinkArrowSymbol>Arrow</SinkArrowSymbol>
+ <zIndex>0</zIndex>
+ </CyTransition>
+ </CyTransitions>
+</Root> \ No newline at end of file
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 15:12:34 +0000