5 files changed, 5 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/addsub.yml b/host/include/uhd/rfnoc/blocks/addsub.yml
index 6e1bd671e..455d065a3 100644
--- a/host/include/uhd/rfnoc/blocks/addsub.yml
+++ b/host/include/uhd/rfnoc/blocks/addsub.yml
@@ -4,6 +4,7 @@ version: 1.0
 rfnoc_version: 1.0
 chdr_width: 64
 noc_id: 0xADD00000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_addsub/Makefile.srcs"
 
 parameters:
   USE_IMPL: '"Verilog"'
diff --git a/host/include/uhd/rfnoc/blocks/fir_filter.yml b/host/include/uhd/rfnoc/blocks/fir_filter.yml
index 4e9281b68..96863653b 100644
--- a/host/include/uhd/rfnoc/blocks/fir_filter.yml
+++ b/host/include/uhd/rfnoc/blocks/fir_filter.yml
@@ -4,6 +4,7 @@ version: 1.0
 rfnoc_version: 1.0
 chdr_width: 64
 noc_id: 0xF1120000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_fir_filter/Makefile.srcs"
 
 parameters:
   NUM_PORTS: 1
diff --git a/host/include/uhd/rfnoc/blocks/fosphor.yml b/host/include/uhd/rfnoc/blocks/fosphor.yml
index 8890e1f90..caa05a796 100644
--- a/host/include/uhd/rfnoc/blocks/fosphor.yml
+++ b/host/include/uhd/rfnoc/blocks/fosphor.yml
@@ -4,6 +4,7 @@ version: 1.0
 rfnoc_version: 1.0
 chdr_width: 64
 noc_id: 0x666F0000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_fosphor/Makefile.srcs"
 
 clocks:
   - name: rfnoc_chdr
diff --git a/host/include/uhd/rfnoc/blocks/split_stream.yml b/host/include/uhd/rfnoc/blocks/split_stream.yml
index 0fdabbe0b..d81fde580 100644
--- a/host/include/uhd/rfnoc/blocks/split_stream.yml
+++ b/host/include/uhd/rfnoc/blocks/split_stream.yml
@@ -4,6 +4,7 @@ version: 1.0
 rfnoc_version: 1.0
 chdr_width: 64
 noc_id: 0x57570000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_split_stream/Makefile.srcs"
 
 parameters:
   NUM_PORTS: 1
diff --git a/host/include/uhd/rfnoc/blocks/vector_iir.yml b/host/include/uhd/rfnoc/blocks/vector_iir.yml
index e04c832d6..40f3f30e2 100644
--- a/host/include/uhd/rfnoc/blocks/vector_iir.yml
+++ b/host/include/uhd/rfnoc/blocks/vector_iir.yml
@@ -4,6 +4,7 @@ version: 1.0
 rfnoc_version: 1.0
 chdr_width: 64
 noc_id: 0x11120000
+makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_vector_iir/Makefile.srcs"
 
 parameters:
   NUM_PORTS: 1