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| author | Matt Ettus <matt@ettus.com> | 2009-12-14 19:54:45 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-14 19:54:45 -0800 |
| commit | c64129bf5dcd9970fd6f70254ef3b93b662ca12f (patch) | |
| tree | 89bf9bd7d5f5ca6febcc41e92804fd3775581041 /vrt | |
| parent | 251b01d424da9612ef827fa5f13d61515d09a354 (diff) | |
| download | uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.tar.gz uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.tar.bz2 uhd-c64129bf5dcd9970fd6f70254ef3b93b662ca12f.zip | |
dsp_core_tx now has setting reg base settable from u2_core. underrun bug in vrt fixed
Diffstat (limited to 'vrt')
| -rw-r--r-- | vrt/vita_tx_control.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index 689acd708..919ded4df 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -62,7 +62,7 @@ module vita_tx_control if(strobe) if(~sample_fifo_src_rdy_i) ibs_state <= IBS_UNDERRUN; - else if(eob) + else if(eop & eob) ibs_state <= IBS_IDLE; // else if(eop) FIXME do we care if the packet ends? |