From c64129bf5dcd9970fd6f70254ef3b93b662ca12f Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Mon, 14 Dec 2009 19:54:45 -0800
Subject: dsp_core_tx now has setting reg base settable from u2_core.  underrun
 bug in vrt fixed

---
 vrt/vita_tx_control.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'vrt')

diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index 689acd708..919ded4df 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -62,7 +62,7 @@ module vita_tx_control
 	   if(strobe)
 	     if(~sample_fifo_src_rdy_i)
 	       ibs_state <= IBS_UNDERRUN;
-	     else if(eob)
+	     else if(eop & eob)
 	       ibs_state <= IBS_IDLE;
 	     // else if(eop)  FIXME do we care if the packet ends?
 
-- 
cgit v1.2.3