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| author | Matt Ettus <matt@ettus.com> | 2009-12-11 18:32:06 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-11 18:32:06 -0800 |
| commit | f346a6137c48821be7f410e7d07a648b5c5e042e (patch) | |
| tree | 77dd73c9eda4a7183d5b478a6bd809cc9024c6e1 /vrt/vita_tx_control.v | |
| parent | 5810c31b4ef73c97ea3ffb0a1ecccb254e141645 (diff) | |
| download | uhd-f346a6137c48821be7f410e7d07a648b5c5e042e.tar.gz uhd-f346a6137c48821be7f410e7d07a648b5c5e042e.tar.bz2 uhd-f346a6137c48821be7f410e7d07a648b5c5e042e.zip | |
put new setting reg into the address space in the right place
Diffstat (limited to 'vrt/vita_tx_control.v')
| -rw-r--r-- | vrt/vita_tx_control.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index 2af68c073..418bd1850 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -42,7 +42,7 @@ module vita_tx_control reg [2:0] ibs_state; wire clear_state; - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 + setting_reg #(.my_addr(BASE+3)) sr (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); |