From f346a6137c48821be7f410e7d07a648b5c5e042e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 11 Dec 2009 18:32:06 -0800 Subject: put new setting reg into the address space in the right place --- vrt/vita_tx_control.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'vrt/vita_tx_control.v') diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v index 2af68c073..418bd1850 100644 --- a/vrt/vita_tx_control.v +++ b/vrt/vita_tx_control.v @@ -42,7 +42,7 @@ module vita_tx_control reg [2:0] ibs_state; wire clear_state; - setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3 + setting_reg #(.my_addr(BASE+3)) sr (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_state)); -- cgit v1.2.3