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| author | Matt Ettus <matt@ettus.com> | 2009-12-08 22:58:49 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-08 22:58:49 -0800 |
| commit | 2de05770dfa11bfbe787a9d9e442d898980fb06a (patch) | |
| tree | d8094d9a4c26d754210e991cf1eb35f7921d9659 /vrt/vita_rx.build | |
| parent | f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5 (diff) | |
| download | uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.tar.gz uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.tar.bz2 uhd-2de05770dfa11bfbe787a9d9e442d898980fb06a.zip | |
make the testbench work in this environment, without the crossclock settings bus
Diffstat (limited to 'vrt/vita_rx.build')
| -rwxr-xr-x | vrt/vita_rx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_rx.build b/vrt/vita_rx.build index e25e1b4e1..f6d2d75a3 100755 --- a/vrt/vita_rx.build +++ b/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |