Merge branch 'ise12' into packet_router

Conflicts:
	usrp2/top/u2_rev3/Makefile
	usrp2/top/u2_rev3/u2_core.v

12 files changed, 241 insertions, 107 deletions

diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 51c006962..33eb2b25a 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -3,27 +3,41 @@
 module time_64bit
   #(parameter TICKS_PER_SEC = 32'd100000000,
     parameter BASE = 0)
-    (input clk, input rst,
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
-     input pps,
-     output [63:0] vita_time, output pps_int
-     );
-
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,  
+    input pps,
+    output [63:0] vita_time, output pps_int,
+    input exp_time_in, output exp_time_out,
+    output [31:0] debug
+    );
+   
    localparam 	   NEXT_SECS = 0;   
    localparam 	   NEXT_TICKS = 1;
    localparam      PPS_POLSRC = 2;
    localparam      PPS_IMM = 3;
    localparam      TPS = 4;
+   localparam      MIMO_SYNC = 5;
    
    reg [31:0] 	   seconds, ticks;
    wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
+   wire [63:0] 	   vita_time_rcvd;
    
    wire [31:0] 	   next_ticks_preset, next_seconds_preset;
    wire [31:0] 	   ticks_per_sec_reg;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
    wire 	   pps_polarity, pps_source, set_imm;
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
+
+   reg [15:0] 	   sync_counter;
+   wire 	   sync_rcvd;
+   wire [31:0] 	   mimo_secs, mimo_ticks;
+   wire 	   mimo_sync_now;
+   wire 	   mimo_sync;
+   wire [7:0] 	   sync_delay;
    
    setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -45,10 +59,10 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(ticks_per_sec_reg),.changed());
 
-   reg [1:0] 	   pps_del;
-   reg 		   pps_reg_p, pps_reg_n, pps_reg;
-   wire 	   pps_edge;
-   
+   setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({mimo_sync,sync_delay}),.changed());
+
    always @(posedge clk)  pps_reg_p <= pps;   
    always @(negedge clk)  pps_reg_n <= pps;
    always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
@@ -82,6 +96,11 @@ module time_64bit
 	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
        end
+     else if(mimo_sync_now)
+       begin
+	  seconds <= mimo_secs;
+	  ticks <= mimo_ticks;
+       end
      else if(ticks_plus_one == ticks_per_sec_reg)
        begin
 	  seconds <= seconds + 1;
@@ -91,5 +110,36 @@ module time_64bit
        ticks <= ticks_plus_one;
 
    assign pps_int = pps_edge;
+
+   // MIMO Connector Time Sync
+   wire send_sync = (sync_counter == 59999); // X % 10 = 9
+
+   always @(posedge clk)
+     if(rst)
+       sync_counter <= 0;
+     else
+       if(send_sync)
+	 sync_counter <= 0;
+       else
+	 sync_counter <= sync_counter + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time),
+      .send_sync(send_sync),
+      .exp_time_out(exp_time_out) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time_rcvd),
+      .sync_rcvd(sync_rcvd),
+      .exp_time_in(exp_time_in) );
+
+   assign mimo_secs = vita_time_rcvd[63:32];
+   assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
+   assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+
+   assign debug = { { 24'b0} ,
+		    { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
    
 endmodule // time_64bit
diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v
index 8e7d3f1ea..fd8651d29 100644
--- a/usrp2/timing/time_receiver.v
+++ b/usrp2/timing/time_receiver.v
@@ -1,9 +1,9 @@
 
 module time_receiver
   (input clk, input rst,
-   output [31:0] master_time,
-   output sync_rcvd,
-   input exp_pps_in);
+   output reg [63:0] vita_time,
+   output reg sync_rcvd,
+   input exp_time_in);
 
    wire       code_err, disp_err, dispout, complete_word;
    reg 	      disp_reg;
@@ -13,7 +13,7 @@ module time_receiver
    reg [8:0]  dataout_reg;
  	      
    always @(posedge clk)
-     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+     shiftreg <= {exp_time_in, shiftreg[9:1]};
 
    localparam COMMA_0 = 10'h283;
    localparam COMMA_1 = 10'h17c;
@@ -55,40 +55,76 @@ module time_receiver
    localparam STATE_T1 = 2;
    localparam STATE_T2 = 3;
    localparam STATE_T3 = 4;
+   localparam STATE_T4 = 5;
+   localparam STATE_T5 = 6;
+   localparam STATE_T6 = 7;
+   localparam STATE_T7 = 8;
+   localparam STATE_TAIL = 9;
    
    localparam HEAD = 9'h13c;   
-
-   reg [7:0]  clock_a, clock_b, clock_c;
-   reg [2:0]  state;
+   localparam TAIL = 9'h1F7;
+   
+   reg [3:0]  state;
    
    always @(posedge clk)
      if(rst)
        state <= STATE_IDLE;
      else if(complete_word)
-       case(state)
-	 STATE_IDLE :
-	   if(dataout_reg == HEAD)
-	     state <= STATE_T0;
-	 STATE_T0 :
-	   begin
-	      clock_a <= dataout_reg[7:0];
-	      state <= STATE_T1;
-	   end
-	 STATE_T1 :
-	   begin
-	      clock_b <= dataout_reg[7:0];
-	      state <= STATE_T2;
-	   end
-	 STATE_T2 :
-	   begin
-	      clock_c <= dataout_reg[7:0];
-	      state <= STATE_T3;
-	   end
-	 STATE_T3 :
-	   state <= STATE_IDLE;
-       endcase // case(state)
-
-   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-   assign sync_rcvd = (complete_word & (state == STATE_T3));
-
+       if(code_err | disp_err)
+	 state <= STATE_IDLE;
+       else
+	 case(state)
+	   STATE_IDLE :
+	     if(dataout_reg == HEAD)
+	       state <= STATE_T0;
+	   STATE_T0 :
+	     begin
+		vita_time[63:56] <= dataout_reg[7:0];
+		state <= STATE_T1;
+	     end
+	   STATE_T1 :
+	     begin
+		vita_time[55:48] <= dataout_reg[7:0];
+		state <= STATE_T2;
+	     end
+	   STATE_T2 :
+	     begin
+		vita_time[47:40] <= dataout_reg[7:0];
+		state <= STATE_T3;
+	     end
+	   STATE_T3 :
+	     begin
+		vita_time[39:32] <= dataout_reg[7:0];
+		state <= STATE_T4;
+	     end
+	   STATE_T4 :
+	     begin
+		vita_time[31:24] <= dataout_reg[7:0];
+		state <= STATE_T5;
+	     end
+	   STATE_T5 :
+	     begin
+		vita_time[23:16] <= dataout_reg[7:0];
+		state <= STATE_T6;
+	     end
+	   STATE_T6 :
+	     begin
+		vita_time[15:8] <= dataout_reg[7:0];
+		state <= STATE_T7;
+	     end
+	   STATE_T7 :
+	     begin
+		vita_time[7:0] <= dataout_reg[7:0];
+		state <= STATE_TAIL;
+	     end
+	   STATE_TAIL :
+	     state <= STATE_IDLE;
+	 endcase // case(state)
+   
+   always @(posedge clk)
+     if(rst)
+       sync_rcvd <= 0;
+     else
+       sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+   
 endmodule // time_sender
diff --git a/usrp2/timing/time_sender.v b/usrp2/timing/time_sender.v
index aa2fcbbdb..f4ee5226a 100644
--- a/usrp2/timing/time_sender.v
+++ b/usrp2/timing/time_sender.v
@@ -2,23 +2,23 @@
 
 module time_sender
   (input clk, input rst,
-   input [31:0] master_time,
+   input [63:0] vita_time,
    input send_sync,
-   output exp_pps_out);
+   output reg exp_time_out);
 
    reg [7:0] datain;
    reg 	     k;
    wire [9:0] dataout;
-   reg [9:0] dataout_reg;
-   reg 	     disp_reg;
-   wire      disp, new_word;
+   reg [9:0]  dataout_reg;
+   reg 	      disp_reg;
+   wire       disp, new_word;
+   reg [4:0]  state;
+   reg [3:0]  bit_count;
    
    encode_8b10b encode_8b10b 
      (.datain({k,datain}),.dispin(disp_reg),
       .dataout(dataout),.dispout(disp));
 
-   assign    exp_pps_out = dataout_reg[0];
-
    always @(posedge clk)
      if(rst)
        disp_reg <= 0;
@@ -33,9 +33,9 @@ module time_sender
      else
        dataout_reg <= {1'b0,dataout_reg[9:1]};
    
-   reg [4:0] state;
-   reg [3:0] bit_count;
-
+   always @(posedge clk)
+     exp_time_out <= dataout_reg[0];
+   
    assign    new_word = (bit_count == 9);
    
    always @(posedge clk)
@@ -52,17 +52,23 @@ module time_sender
    localparam SEND_T1 = 3;
    localparam SEND_T2 = 4;
    localparam SEND_T3 = 5;
+   localparam SEND_T4 = 6;
+   localparam SEND_T5 = 7;
+   localparam SEND_T6 = 8;
+   localparam SEND_T7 = 9;
+   localparam SEND_TAIL = 10;
 
    localparam COMMA = 8'hBC;
    localparam HEAD = 8'h3C;
-
-   reg [31:0] master_time_reg;
+   localparam TAIL = 8'hF7;
+   
+   reg [63:0] vita_time_reg;
    
    always @(posedge clk)
      if(rst)
-       master_time_reg <= 0;
+       vita_time_reg <= 0;
      else if(send_sync)
-       master_time_reg <= master_time;
+       vita_time_reg <= vita_time;
    
    always @(posedge clk)
      if(rst)
@@ -84,27 +90,51 @@ module time_sender
 	     end
 	   SEND_T0 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[31:24] };
+		{k,datain} <= {1'b0, vita_time_reg[63:56] };
 		state <= SEND_T1;
 	     end
 	   SEND_T1 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[23:16]};
+		{k,datain} <= {1'b0, vita_time_reg[55:48]};
 		state <= SEND_T2;
 	     end
 	   SEND_T2 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[15:8]};
+		{k,datain} <= {1'b0, vita_time_reg[47:40]};
 		state <= SEND_T3;
 	     end
 	   SEND_T3 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[7:0]};
+		{k,datain} <= {1'b0, vita_time_reg[39:32]};
+		state <= SEND_T4;
+	     end
+	   SEND_T4 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[31:24]};
+		state <= SEND_T5;
+	     end
+	   SEND_T5 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[23:16]};
+		state <= SEND_T6;
+	     end
+	   SEND_T6 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[15:8]};
+		state <= SEND_T7;
+	     end
+	   SEND_T7 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[7:0]};
+		state <= SEND_TAIL;
+	     end
+	   SEND_TAIL :
+	     begin
+		{k,datain} <= {1'b1, TAIL};
 		state <= SEND_IDLE;
 	     end
 	   default :
 	     state <= SEND_IDLE;
 	 endcase // case(state)
    
-   
 endmodule // time_sender
diff --git a/usrp2/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v
index 2b75c60bd..0c164f82c 100644
--- a/usrp2/timing/time_transfer_tb.v
+++ b/usrp2/timing/time_transfer_tb.v
@@ -18,12 +18,12 @@ module time_transfer_tb();
    
    initial #100000000 $finish;
 
-   wire exp_pps, pps, pps_rcv;
-   wire [31:0] master_clock_rcv;
-   reg [31:0]  master_clock = 0;
-   reg [31:0]  counter = 0;
+   wire exp_time, pps, pps_rcv;
+   wire [63:0] vita_time_rcv;
+   reg [63:0]  vita_time = 0;
+   reg [63:0]  counter = 0;
 
-   localparam  PPS_PERIOD = 109;
+   localparam  PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
    always @(posedge clk)
      if(counter == PPS_PERIOD)
        counter <= 0;
@@ -32,19 +32,19 @@ module time_transfer_tb();
    assign      pps = (counter == (PPS_PERIOD-1));
    
    always @(posedge clk)
-     master_clock <= master_clock + 1;
+     vita_time <= vita_time + 1;
    
    time_sender time_sender
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock),
-      .pps(pps),
-      .exp_pps_out(exp_pps) );
+      .vita_time(vita_time),
+      .send_sync(pps),
+      .exp_time_out(exp_time) );
 
    time_receiver time_receiver
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock_rcv),
-      .pps(pps_rcv),
-      .exp_pps_in(exp_pps) );
+      .vita_time(vita_time_rcv),
+      .sync_rcvd(pps_rcv),
+      .exp_time_in(exp_time) );
 
-   wire [31:0] delta = master_clock - master_clock_rcv;
+   wire [31:0] delta = vita_time - vita_time_rcv;
 endmodule // time_transfer_tb
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 99effb038..05ada2476 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -6,7 +6,7 @@
 # Project Setup
 ##################################################
 TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build-udp$(ISE))
+BUILD_DIR = $(abspath build)
 
 ##################################################
 # Include other makefiles
@@ -46,7 +46,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 # Sources
 ##################################################
 TOP_SRCS = \
-u2_core_udp.v \
+u2_core.v \
 u2_rev3.v \
 u2_rev3.ucf
 
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index c85e81140..363ac3635 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -17,8 +17,8 @@ module u2_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -431,7 +431,6 @@ module u2_core
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-      
       .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
@@ -721,10 +720,14 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
+   wire [31:0] 	 debug_sync;
+   
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
-   
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
+      .debug(debug_sync));
+
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 6e0caedd5..8017f61ff 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -40,10 +40,10 @@ NET "debug_clk[0]"  LOC = "N4"  ;
 NET "debug_clk[1]"  LOC = "M1"  ;
 NET "uart_tx_o"  LOC = "C7"  ;
 NET "uart_rx_i"  LOC = "A3"  ;
-NET "exp_pps_in_p"  LOC = "V3"  ; 
-NET "exp_pps_in_n"  LOC = "V4"  ; 
-NET "exp_pps_out_p"  LOC = "V1"  ; 
-NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_time_in_p"  LOC = "V3"  ; 
+NET "exp_time_in_n"  LOC = "V4"  ; 
+NET "exp_time_out_p"  LOC = "V1"  ; 
+NET "exp_time_out_n"  LOC = "V2"  ; 
 NET "GMII_COL"  LOC = "U16"  ; 
 NET "GMII_CRS"  LOC = "U17"  ; 
 NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 4f7f9bf1a..f2bba6c50 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -11,10 +11,10 @@ module u2_rev3
    input uart_rx_i,
    
    // Expansion
-   input exp_pps_in_p, // Diff
-   input exp_pps_in_n, // Diff
-   output exp_pps_out_p, // Diff 
-   output exp_pps_out_n, // Diff 
+   input exp_time_in_p, // Diff
+   input exp_time_in_n, // Diff
+   output exp_time_out_p, // Diff 
+   output exp_time_out_n, // Diff 
    
    // GMII
    //   GMII-CTRL
@@ -181,13 +181,13 @@ module u2_rev3
    wire 	cpld_clock_buf;
    BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock));
    
-   wire 	exp_pps_in;
-   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
-   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
    
-   wire 	exp_pps_out;
-   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
-   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD = "LVDS_25";
 
    reg [5:0] 	clock_ready_d;
    always @(posedge clk_fpga)
@@ -480,8 +480,8 @@ module u2_rev3
 	     .leds		(leds_int),
 	     .debug		(debug[31:0]),
 	     .debug_clk		(debug_clk[1:0]),
-	     .exp_pps_in	(exp_pps_in),
-	     .exp_pps_out	(exp_pps_out),
+	     .exp_time_in	(exp_time_in),
+	     .exp_time_out	(exp_time_out),
 	     .GMII_COL		(GMII_COL),
 	     .GMII_CRS		(GMII_CRS),
 	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 25267a67e..5fbe55c26 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -158,7 +158,7 @@ NET "RXD<2>"  LOC = "AF15"  ;
 NET "RXD<1>"  LOC = "AD12"  ;
 
 ## AD9510
-NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "clk_status"  LOC = "AD22"  ;
 NET "CLK_FUNC"  LOC = "AC21"  ;
 NET "clk_sel<0>"  LOC = "AE21"  ;
 NET "clk_sel<1>"  LOC = "AD21"  ;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 270655a8d..c0140e989 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -44,7 +44,7 @@ module u2plus
    output [1:0] clk_en,
    output [1:0] clk_sel,
    input CLK_FUNC,        // FIXME is an input to control the 9510
-   input CLK_STATUS,
+   input clk_status,
 
    inout SCL, inout SDA,   // I2C
 
@@ -357,8 +357,8 @@ module u2plus
 		     .leds		(leds_int),
 		     .debug		(debug[31:0]),
 		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_time_in),
-		     .exp_pps_out	(exp_time_out),
+		     .exp_time_in	(exp_time_in),
+		     .exp_time_out	(exp_time_out),
 		     .GMII_COL		(GMII_COL),
 		     .GMII_CRS		(GMII_CRS),
 		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 8426826e2..4e0b190ef 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -16,8 +16,8 @@ module u2plus_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -683,7 +683,8 @@ module u2plus_core
 
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out));
    
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index 20ad6b995..ab6da8bd0 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -40,7 +40,21 @@ module vita_tx_control
    time_compare 
      time_compare (.time_now(vita_time), .trigger_time(send_time), 
 		   .now(now), .early(early), .late(late), .too_early());
+
+   reg 	       late_qual, late_del;
+
+   always @(posedge clk)
+     if(reset | clear)
+       late_del <= 0;
+     else
+       late_del <= late;
    
+   always @(posedge clk)
+     if(reset | clear)
+       late_qual <= 0;
+     else
+       late_qual <= (sample_fifo_src_rdy_i & ~sample_fifo_dst_rdy_o);
+      
    localparam IBS_IDLE = 0;
    localparam IBS_RUN = 1;  // FIXME do we need this?
    localparam IBS_CONT_BURST = 2;
@@ -87,7 +101,7 @@ module vita_tx_control
 	       end
 	     else if(~send_at | now)
 	       ibs_state <= IBS_RUN;
-	     else if(late | too_early)
+	     else if((late_qual & late_del) | too_early)
 	       begin
 		  ibs_state <= IBS_ERROR;
 		  error_code <= CODE_TIME_ERROR;
@@ -166,7 +180,7 @@ module vita_tx_control
      else
        packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o;
    
-   assign debug = { { now,early,late,ack,eop,eob,sob,send_at },
+   assign debug = { { now,late_qual,late_del,ack,eop,eob,sob,send_at },
 		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
 		    { 8'b0 },
 		    { 8'b0 } };