Merge branch 'ise12' into packet_router

Conflicts:
	usrp2/top/u2_rev3/Makefile
	usrp2/top/u2_rev3/u2_core.v

7 files changed, 34 insertions, 30 deletions

diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 99effb038..05ada2476 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -6,7 +6,7 @@
 # Project Setup
 ##################################################
 TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build-udp$(ISE))
+BUILD_DIR = $(abspath build)
 
 ##################################################
 # Include other makefiles
@@ -46,7 +46,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 # Sources
 ##################################################
 TOP_SRCS = \
-u2_core_udp.v \
+u2_core.v \
 u2_rev3.v \
 u2_rev3.ucf
 
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index c85e81140..363ac3635 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -17,8 +17,8 @@ module u2_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -431,7 +431,6 @@ module u2_core
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-      
       .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
@@ -721,10 +720,14 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
+   wire [31:0] 	 debug_sync;
+   
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
-   
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
+      .debug(debug_sync));
+
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 6e0caedd5..8017f61ff 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -40,10 +40,10 @@ NET "debug_clk[0]"  LOC = "N4"  ;
 NET "debug_clk[1]"  LOC = "M1"  ;
 NET "uart_tx_o"  LOC = "C7"  ;
 NET "uart_rx_i"  LOC = "A3"  ;
-NET "exp_pps_in_p"  LOC = "V3"  ; 
-NET "exp_pps_in_n"  LOC = "V4"  ; 
-NET "exp_pps_out_p"  LOC = "V1"  ; 
-NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_time_in_p"  LOC = "V3"  ; 
+NET "exp_time_in_n"  LOC = "V4"  ; 
+NET "exp_time_out_p"  LOC = "V1"  ; 
+NET "exp_time_out_n"  LOC = "V2"  ; 
 NET "GMII_COL"  LOC = "U16"  ; 
 NET "GMII_CRS"  LOC = "U17"  ; 
 NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 4f7f9bf1a..f2bba6c50 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -11,10 +11,10 @@ module u2_rev3
    input uart_rx_i,
    
    // Expansion
-   input exp_pps_in_p, // Diff
-   input exp_pps_in_n, // Diff
-   output exp_pps_out_p, // Diff 
-   output exp_pps_out_n, // Diff 
+   input exp_time_in_p, // Diff
+   input exp_time_in_n, // Diff
+   output exp_time_out_p, // Diff 
+   output exp_time_out_n, // Diff 
    
    // GMII
    //   GMII-CTRL
@@ -181,13 +181,13 @@ module u2_rev3
    wire 	cpld_clock_buf;
    BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock));
    
-   wire 	exp_pps_in;
-   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
-   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
    
-   wire 	exp_pps_out;
-   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
-   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD = "LVDS_25";
 
    reg [5:0] 	clock_ready_d;
    always @(posedge clk_fpga)
@@ -480,8 +480,8 @@ module u2_rev3
 	     .leds		(leds_int),
 	     .debug		(debug[31:0]),
 	     .debug_clk		(debug_clk[1:0]),
-	     .exp_pps_in	(exp_pps_in),
-	     .exp_pps_out	(exp_pps_out),
+	     .exp_time_in	(exp_time_in),
+	     .exp_time_out	(exp_time_out),
 	     .GMII_COL		(GMII_COL),
 	     .GMII_CRS		(GMII_CRS),
 	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 25267a67e..5fbe55c26 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -158,7 +158,7 @@ NET "RXD<2>"  LOC = "AF15"  ;
 NET "RXD<1>"  LOC = "AD12"  ;
 
 ## AD9510
-NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "clk_status"  LOC = "AD22"  ;
 NET "CLK_FUNC"  LOC = "AC21"  ;
 NET "clk_sel<0>"  LOC = "AE21"  ;
 NET "clk_sel<1>"  LOC = "AD21"  ;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 270655a8d..c0140e989 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -44,7 +44,7 @@ module u2plus
    output [1:0] clk_en,
    output [1:0] clk_sel,
    input CLK_FUNC,        // FIXME is an input to control the 9510
-   input CLK_STATUS,
+   input clk_status,
 
    inout SCL, inout SDA,   // I2C
 
@@ -357,8 +357,8 @@ module u2plus
 		     .leds		(leds_int),
 		     .debug		(debug[31:0]),
 		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_time_in),
-		     .exp_pps_out	(exp_time_out),
+		     .exp_time_in	(exp_time_in),
+		     .exp_time_out	(exp_time_out),
 		     .GMII_COL		(GMII_COL),
 		     .GMII_CRS		(GMII_CRS),
 		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 8426826e2..4e0b190ef 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -16,8 +16,8 @@ module u2plus_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -683,7 +683,8 @@ module u2plus_core
 
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out));
    
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins