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| author | Josh Blum <josh@joshknows.com> | 2012-07-02 12:56:22 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-07-02 12:56:22 -0700 |
| commit | 295c7e7b98df98989f3fb4505e44f0be52813d81 (patch) | |
| tree | c4f9b219d198cecd06c7091680ce7ad47ff3430d /usrp2/top/B100/core_compile | |
| parent | c19e10d790e99cc555510cb121437ba56278c3f6 (diff) | |
| download | uhd-295c7e7b98df98989f3fb4505e44f0be52813d81.tar.gz uhd-295c7e7b98df98989f3fb4505e44f0be52813d81.tar.bz2 uhd-295c7e7b98df98989f3fb4505e44f0be52813d81.zip | |
B100: squash B100 top level work
Implements timed commands and FIFO control.
Uses control and data FIFOs for GPIF.
Implements a common core for E100/B100.
Diffstat (limited to 'usrp2/top/B100/core_compile')
| -rwxr-xr-x | usrp2/top/B100/core_compile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile index b62cbaee0..2192bfa94 100755 --- a/usrp2/top/B100/core_compile +++ b/usrp2/top/B100/core_compile @@ -1 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |