From 295c7e7b98df98989f3fb4505e44f0be52813d81 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 2 Jul 2012 12:56:22 -0700 Subject: B100: squash B100 top level work Implements timed commands and FIFO control. Uses control and data FIFOs for GPIF. Implements a common core for E100/B100. --- usrp2/top/B100/core_compile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'usrp2/top/B100/core_compile') diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile index b62cbaee0..2192bfa94 100755 --- a/usrp2/top/B100/core_compile +++ b/usrp2/top/B100/core_compile @@ -1 +1 @@ -iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models +iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models -- cgit v1.2.3