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| author | Matt Ettus <matt@ettus.com> | 2010-05-18 12:18:31 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-18 12:18:31 -0700 |
| commit | b9257e64be63429099186cdb1a3eaff0a325ffb7 (patch) | |
| tree | 606d18e7f924d4dd9b5ca3a4c4e931ad0e02a580 /usrp2/opencores/aemb/rtl | |
| parent | 5b449a1ca7aabd5b0201aca069ef088cdca25da7 (diff) | |
| download | uhd-b9257e64be63429099186cdb1a3eaff0a325ffb7.tar.gz uhd-b9257e64be63429099186cdb1a3eaff0a325ffb7.tar.bz2 uhd-b9257e64be63429099186cdb1a3eaff0a325ffb7.zip | |
added pragmas suggested by Ian Buckley to help ISE12 synthesis
Diffstat (limited to 'usrp2/opencores/aemb/rtl')
| -rw-r--r-- | usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v index 9ac45299b..7fe108957 100644 --- a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v +++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v @@ -146,9 +146,12 @@ module aeMB_regf (/*AUTOARG*/ // LUT RAM implementation is smaller and faster. R0 gets written // during reset with 0x00 and doesn't change after. - reg [31:0] mARAM[0:31], - mBRAM[0:31], - mDRAM[0:31]; + //synthesis attribute ram_style of mARAM is distributed + reg [31:0] mARAM[0:31]; + //synthesis attribute ram_style of mBRAM is distributed + reg [31:0] mBRAM[0:31]; + //synthesis attribute ram_style of mDRAM is distributed + reg [31:0] mDRAM[0:31]; wire [31:0] rREGW = mDRAM[rRW]; wire [31:0] rREGD = mDRAM[rRD]; |