added pragmas suggested by Ian Buckley to help ISE12 synthesis

1 files changed, 6 insertions, 3 deletions

diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
index 9ac45299b..7fe108957 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
@@ -146,9 +146,12 @@ module aeMB_regf (/*AUTOARG*/
    // LUT RAM implementation is smaller and faster. R0 gets written
    // during reset with 0x00 and doesn't change after.
    
-   reg [31:0] 	 mARAM[0:31],
-		 mBRAM[0:31],
-		 mDRAM[0:31];
+   //synthesis attribute ram_style of mARAM is distributed
+   reg [31:0] 	 mARAM[0:31]; 
+   //synthesis attribute ram_style of mBRAM is distributed
+   reg [31:0] 	 mBRAM[0:31];
+   //synthesis attribute ram_style of mDRAM is distributed
+   reg [31:0] 	 mDRAM[0:31];
 
    wire [31:0] 	 rREGW = mDRAM[rRW];   
    wire [31:0] 	 rREGD = mDRAM[rRD];