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| author | Matt Ettus <matt@ettus.com> | 2010-07-14 17:01:25 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 11:36:09 -0800 |
| commit | d0742cf2a5285ed08d49e16948d8227414247f6a (patch) | |
| tree | 90b00baeee5abed47cc61d7c34619743584a4f02 /usrp2/extramfifo/fifo_extram36_tb.build | |
| parent | f9db9f4eed98a7538d73b5463e762441198526c1 (diff) | |
| download | uhd-d0742cf2a5285ed08d49e16948d8227414247f6a.tar.gz uhd-d0742cf2a5285ed08d49e16948d8227414247f6a.tar.bz2 uhd-d0742cf2a5285ed08d49e16948d8227414247f6a.zip | |
get it to build
Diffstat (limited to 'usrp2/extramfifo/fifo_extram36_tb.build')
| -rwxr-xr-x[-rw-r--r--] | usrp2/extramfifo/fifo_extram36_tb.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build index 699591889..ac9369758 100644..100755 --- a/usrp2/extramfifo/fifo_extram36_tb.build +++ b/usrp2/extramfifo/fifo_extram36_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v |