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| author | Matt Ettus <matt@ettus.com> | 2011-06-12 14:03:42 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-12 14:03:42 -0700 |
| commit | cd9308eb81fd37fcd5142d49c10741f107e6b657 (patch) | |
| tree | 42a80b07cd7d438330c6e7875a367c59cc6f3b93 /usrp2/coregen/coregen.cgp | |
| parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
| download | uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.tar.gz uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.tar.bz2 uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.zip | |
u1e: new 2 clock fifo, 18 bits by 1K
Diffstat (limited to 'usrp2/coregen/coregen.cgp')
| -rw-r--r-- | usrp2/coregen/coregen.cgp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp index dd85a7f50..01d31bf5b 100644 --- a/usrp2/coregen/coregen.cgp +++ b/usrp2/coregen/coregen.cgp @@ -1,5 +1,4 @@ -# Date: Fri Oct 15 07:50:19 2010 - +# Date: Fri Jun 10 23:12:37 2011 SET addpads = false SET asysymbol = false SET busformat = BusFormatAngleBracketNotRipped @@ -19,4 +18,3 @@ SET verilogsim = true SET vhdlsim = false SET workingdirectory = /tmp/ -# CRC: 983b9b45 |