From cd9308eb81fd37fcd5142d49c10741f107e6b657 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Sun, 12 Jun 2011 14:03:42 -0700
Subject: u1e: new 2 clock fifo, 18 bits by 1K

---
 usrp2/coregen/coregen.cgp | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'usrp2/coregen/coregen.cgp')

diff --git a/usrp2/coregen/coregen.cgp b/usrp2/coregen/coregen.cgp
index dd85a7f50..01d31bf5b 100644
--- a/usrp2/coregen/coregen.cgp
+++ b/usrp2/coregen/coregen.cgp
@@ -1,5 +1,4 @@
-# Date: Fri Oct 15 07:50:19 2010
-
+# Date: Fri Jun 10 23:12:37 2011
 SET addpads = false
 SET asysymbol = false
 SET busformat = BusFormatAngleBracketNotRipped
@@ -19,4 +18,3 @@ SET verilogsim = true
 SET vhdlsim = false
 SET workingdirectory = /tmp/
 
-# CRC: 983b9b45
-- 
cgit v1.2.3