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| author | Matt Ettus <matt@ettus.com> | 2010-03-26 11:30:13 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-26 11:30:13 -0700 |
| commit | 7a3064b67172aea1be00d188bdd79185a7df2ecf (patch) | |
| tree | 3be087c9d1a37a855fa54097d751b92053c16af5 /usrp1/tb/justinterp_tb.v | |
| parent | f979a9d4e7b9664e046aaca54357e46782c4aa51 (diff) | |
| download | uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.tar.gz uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.tar.bz2 uhd-7a3064b67172aea1be00d188bdd79185a7df2ecf.zip | |
connect 2 clock gen controls and 3 status pins to the wishbone so they can be read/controlled from SW
Diffstat (limited to 'usrp1/tb/justinterp_tb.v')
0 files changed, 0 insertions, 0 deletions