uio: mpm: Fixup for opening mboard-regs UIO

- Fix the syntax to open mboard-regs UIO objects, and change the open()
and close() functions to be private.
- We were calling open() twice in every context manager line- once
manually, and once in __enter__. This commit corrects those usages, and
allows the context manager to fully manage the opening and closing of
UIO objects.

7 files changed, 71 insertions, 62 deletions

diff --git a/mpm/python/usrp_mpm/cores/white_rabbit.py b/mpm/python/usrp_mpm/cores/white_rabbit.py
index c30c325e9..eeeb5fd31 100644
--- a/mpm/python/usrp_mpm/cores/white_rabbit.py
+++ b/mpm/python/usrp_mpm/cores/white_rabbit.py
@@ -45,7 +45,7 @@ class WhiteRabbitRegsControl(object):
         """
         Retrieves and decodes the lock status for the PPS out of the WR core.
         """
-        with self.regs.open():
+        with self.regs:
             ext_sync_status = self.periph_peek32(self.PPSG_ESCR)
         # bit 2: PPS_VALID
         # bit 3: TM_VALID (timecode)
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index 808417f0c..341af86b8 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -190,7 +190,7 @@ class DboardClockControl(object):
         """
         Enables or disables the MMCM outputs.
         """
-        with self.regs.open():
+        with self.regs:
             if enable:
                 self.poke32(self.RADIO_CLK_ENABLES, 0x011)
             else:
@@ -202,7 +202,7 @@ class DboardClockControl(object):
         """
         self.log.trace("Disabling all Radio Clocks, then resetting MMCM...")
         self.enable_outputs(False)
-        with self.regs.open():
+        with self.regs:
             self.poke32(self.RADIO_CLK_MMCM, 0x1)
 
     def enable_mmcm(self):
@@ -212,7 +212,7 @@ class DboardClockControl(object):
         If MMCM is not locked after unreset, an exception is thrown.
         """
         self.log.trace("Un-resetting MMCM...")
-        with self.regs.open():
+        with self.regs:
             self.poke32(self.RADIO_CLK_MMCM, 0x2)
             time.sleep(0.5) # Replace with poll and timeout TODO
             mmcm_locked = bool(self.peek32(self.RADIO_CLK_MMCM) & 0x10)
@@ -226,7 +226,7 @@ class DboardClockControl(object):
         """
         Not technically a clocking reg, but related.
         """
-        with self.regs.open():
+        with self.regs:
             return bool(self.peek32(self.MGT_REF_CLK_STATUS) & 0x1)
 
 
@@ -267,7 +267,7 @@ class JesdCoreEiscat(object):
         Verify that the JESD core ID is correct.
         """
         expected_id = self.CORE_ID_BASE + self.core_idx
-        with self.regs.open():
+        with self.regs:
             core_id = self.peek32(self.JESD_SIGNATURE_REG)
             self.log.trace("Reading JESD core ID: {:x}".format(core_id))
             if core_id != expected_id:
@@ -301,7 +301,7 @@ class JesdCoreEiscat(object):
         Returns nothing, but throws on error.
         """
         self.log.trace("Init JESD Deframer...")
-        with self.regs.open():
+        with self.regs:
             self.poke32(0x40, 0x02) # Force assertion of ADC SYNC
             self.poke32(0x50, 0x01) # Data = 0 = Scrambler enabled. Data = 1 = disabled. Must match ADC settings.
             if not self._gt_rx_reset(reset_only=False):
@@ -324,7 +324,7 @@ class JesdCoreEiscat(object):
         """
         Power down unused CPLLs and QPLLs
         """
-        with self.regs.open():
+        with self.regs:
             self.poke32(0x00C, 0xFFFC0000)
             self.log.trace("MGT power enabled readback: {:x}".format(self.peek32(0x00C)))
 
@@ -335,7 +335,7 @@ class JesdCoreEiscat(object):
 
         Returns True on success.
         """
-        with self.regs.open():
+        with self.regs:
             self.poke32(0x024, 0x10) # Place the RX MGTs in reset
             if not reset_only:
                 time.sleep(.001) # Probably not necessary
@@ -355,7 +355,7 @@ class JesdCoreEiscat(object):
         """
         Make sure PLLs are locked
         """
-        with self.regs.open():
+        with self.regs:
             self.poke32(0x004, 0x11111111) # Reset CPLLs
             self.poke32(0x004, 0x11111100) # Unreset the ones we're using
             time.sleep(0.02) # TODO replace with poll and timeout
@@ -379,7 +379,7 @@ class JesdCoreEiscat(object):
             "JESD Core: Slot {}, ADC {}: Setting polarity control to 0x{:2x}".format(
                 self.slot, self.core_idx, reg_val
             ))
-        with self.regs.open():
+        with self.regs:
             self.poke32(0x80, reg_val)
 
 
@@ -593,7 +593,7 @@ class EISCAT(DboardManagerBase):
         fashion though.
         """
         self.log.trace("Sending SYSREF via MPM...")
-        with self.radio_regs.open():
+        with self.radio_regs:
             self.radio_regs.poke32(self.SYSREF_CONTROL, 0x0)
             self.radio_regs.poke32(self.SYSREF_CONTROL, 0x1)
             self.radio_regs.poke32(self.SYSREF_CONTROL, 0x0)
@@ -692,7 +692,7 @@ class EISCAT(DboardManagerBase):
         # Enable all channels first due to a signal integrity issue when enabling them
         # after the LNA enable is asserted.
         self.log.trace("Enabling power to the daughterboard...")
-        with regs.open():
+        with regs:
             regs.poke32(self.DB_CH_ENABLES, 0x000000FF)
             regs.poke32(self.DB_ENABLES,    0x01000000)
             regs.poke32(self.DB_ENABLES,    0x00010101)
@@ -704,7 +704,7 @@ class EISCAT(DboardManagerBase):
         Turn off power to the dboard. Sequence is reverse of init_power.
         """
         self.log.trace("Disabling power to the daughterboard...")
-        with regs.open():
+        with regs:
             regs.poke32(self.ADC_CONTROL,   0x00100000)
             regs.poke32(self.DB_ENABLES,    0x10101010)
             regs.poke32(self.DB_CH_ENABLES, 0x00000000) # Disable all channels (last)
diff --git a/mpm/python/usrp_mpm/ethtable.py b/mpm/python/usrp_mpm/ethtable.py
index e3a3035ec..1721f4724 100644
--- a/mpm/python/usrp_mpm/ethtable.py
+++ b/mpm/python/usrp_mpm/ethtable.py
@@ -41,7 +41,7 @@ class EthDispatcherTable(object):
         """
         self.log.debug("Setting my own IP address to `{}'".format(ip_addr))
         ip_addr_int = int(netaddr.IPAddress(ip_addr))
-        with self._regs.open():
+        with self._regs:
             self.poke32(self.OWN_IP_OFFSET, ip_addr_int)
 
     def set_vita_port(self, port_value=None, port_idx=None):
@@ -53,7 +53,7 @@ class EthDispatcherTable(object):
         port_value = port_value or self.DEFAULT_VITA_PORT[port_idx]
         assert port_idx in (0)                      #FIXME: Fix port_idx = 1
         port_reg_addr = self.OWN_PORT_OFFSET
-        with self._regs.open():
+        with self._regs:
             self.poke32(port_reg_addr, port_value)
 
     def set_route(self, sid, ip_addr, udp_port, mac_addr=None):
@@ -102,7 +102,7 @@ class EthDispatcherTable(object):
             ))
             self.poke32(addr, data)
 
-        with self._regs.open():
+        with self._regs:
             poke_and_trace(
                 self.SID_IP_OFFSET + sid_offset,
                 ip_addr_int
@@ -125,5 +125,5 @@ class EthDispatcherTable(object):
         self.log.trace("Writing to address 0x{:04X}: 0x{:04X}".format(
             self.FORWARD_ETH_BCAST_OFFSET, reg_value
         ))
-        with self._regs.open():
+        with self._regs:
             self.poke32(self.FORWARD_ETH_BCAST_OFFSET, reg_value)
diff --git a/mpm/python/usrp_mpm/liberiotable.py b/mpm/python/usrp_mpm/liberiotable.py
index 19226345b..d732eedcb 100644
--- a/mpm/python/usrp_mpm/liberiotable.py
+++ b/mpm/python/usrp_mpm/liberiotable.py
@@ -47,7 +47,7 @@ class LiberioDispatcherTable(object):
             self.poke32(addr, data)
         # Poke reg for destination channel
         try:
-            with self._regs.open():
+            with self._regs:
                 poke_and_trace(
                     0 + 4 * sid.dst_ep,
                     dma_channel,
diff --git a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py
index ee092e248..eab96a483 100644
--- a/mpm/python/usrp_mpm/periph_manager/e320_periphs.py
+++ b/mpm/python/usrp_mpm/periph_manager/e320_periphs.py
@@ -114,7 +114,7 @@ class MboardRegsControl(object):
         The return is a tuple of
         2 numbers: (major compat number, minor compat number )
         """
-        with self.regs.open():
+        with self.regs:
             compat_number = self.peek32(self.MB_COMPAT_NUM)
         minor = compat_number & 0xff
         major = (compat_number>>16) & 0xff
@@ -132,7 +132,7 @@ class MboardRegsControl(object):
             self.set_fp_gpio_voltage(value)
         mask = 0xFFFFFFFF ^ ((0b1 << self.MB_GPIO_CTRL_BUFFER_OE_N) | \
                              (0b1 << self.MB_GPIO_CTRL_EN_VAR_SUPPLY))
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_GPIO_CTRL) & mask
             reg_val = reg_val | (not enable << self.MB_GPIO_CTRL_BUFFER_OE_N) | \
                                 (enable << self.MB_GPIO_CTRL_EN_VAR_SUPPLY)
@@ -158,7 +158,7 @@ class MboardRegsControl(object):
             voltage_reg = 2
         mask = 0xFFFFFFFF ^ ((0b1 << self.MB_GPIO_CTRL_EN_3V3) | \
                              (0b1 << self.MB_GPIO_CTRL_EN_2V5))
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_GPIO_CTRL) & mask
             reg_val = reg_val | (voltage_reg << self.MB_GPIO_CTRL_EN_2V5)
             self.log.trace("Writing MB_GPIO_CTRL to 0x{:08X}".format(reg_val))
@@ -170,7 +170,7 @@ class MboardRegsControl(object):
         """
         mask = 0x3 << self.MB_GPIO_CTRL_EN_2V5
         voltage = [1.8, 2.5, 3.3]
-        with self.regs.open():
+        with self.regs:
             reg_val = (self.peek32(self.MB_GPIO_CTRL) & mask) >> self.MB_GPIO_CTRL_EN_2V5
         return voltage[reg_val]
 
@@ -179,7 +179,7 @@ class MboardRegsControl(object):
         Arguments:
             value {unsigned} -- value is a single bit bit mask of 8 pins GPIO
         """
-        with self.regs.open():
+        with self.regs:
             return self.poke32(self.MB_GPIO_MASTER, value)
 
     def get_fp_gpio_master(self):
@@ -188,7 +188,7 @@ class MboardRegsControl(object):
            0: means the pin is driven by PL
            1: means the pin is driven by PS
         """
-        with self.regs.open():
+        with self.regs:
             return self.peek32(self.MB_GPIO_MASTER) & 0xfff
 
     def set_fp_gpio_radio_src(self, value):
@@ -198,7 +198,7 @@ class MboardRegsControl(object):
            00: means the pin is driven by radio 0
            01: means the pin is driven by radio 1
         """
-        with self.regs.open():
+        with self.regs:
             return self.poke32(self.MB_GPIO_RADIO_SRC, value)
 
     def get_fp_gpio_radio_src(self):
@@ -207,7 +207,7 @@ class MboardRegsControl(object):
            00: means the pin is driven by radio 0
            01: means the pin is driven by radio 1
         """
-        with self.regs.open():
+        with self.regs:
             return self.peek32(self.MB_GPIO_RADIO_SRC) & 0xffffff
 
     def get_build_timestamp(self):
@@ -216,7 +216,7 @@ class MboardRegsControl(object):
         The return is datetime string with the  ISO 8601 format
         (YYYY-MM-DD HH:MM:SS.mmmmmm)
         """
-        with self.regs.open():
+        with self.regs:
             datestamp_rb = self.peek32(self.MB_DATESTAMP)
         if datestamp_rb > 0:
             dt_str = datetime.datetime(
@@ -238,7 +238,7 @@ class MboardRegsControl(object):
         The return is a tuple of
         2 numbers: (short git hash, bool: is the tree dirty?)
         """
-        with self.regs.open():
+        with self.regs:
             git_hash_rb = self.peek32(self.MB_GIT_HASH)
         git_hash = git_hash_rb & 0x0FFFFFFF
         tree_dirty = ((git_hash_rb & 0xF0000000) > 0)
@@ -261,7 +261,7 @@ class MboardRegsControl(object):
             pps_sel_val = 0b1 << self.MB_CLOCK_CTRL_PPS_SEL_EXT
         else:
             assert False, "Cannot set to invalid time source: {}".format(time_source)
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_CLOCK_CTRL) & 0xFFFFFF90
             # prevent glitches by writing a cleared value first, then the final value.
             self.poke32(self.MB_CLOCK_CTRL, reg_val)
@@ -284,7 +284,7 @@ class MboardRegsControl(object):
         else:
             assert False, "Cannot set to invalid clock source: {}".format(clock_source)
         mask = 0xFFFFFFFF ^ (0b1 << self.MB_CLOCK_CTRL_REF_SEL)
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_CLOCK_CTRL) & mask
             reg_val = reg_val | (ref_sel_val << self.MB_CLOCK_CTRL_REF_SEL)
             self.log.trace("Writing MB_CLOCK_CTRL to 0x{:08X}".format(reg_val))
@@ -295,7 +295,7 @@ class MboardRegsControl(object):
         Reads the type of the FPGA image currently loaded
         Returns a string with the type (ie 1G, XG, AU, etc.)
         """
-        with self.regs.open():
+        with self.regs:
             sfp_info_rb = self.peek32(self.MB_SFP_PORT_INFO)
         # Print the registers values as 32-bit hex values
         self.log.trace("SFP Info: 0x{0:0{1}X}".format(sfp_info_rb, 8))
@@ -313,7 +313,7 @@ class MboardRegsControl(object):
         Get GPS LOCK status
         """
         mask = 0b1 << self.MB_GPS_STATUS_LOCK
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_GPS_STATUS) & mask
             gps_locked = reg_val & 0x1 #FIXME
         if gps_locked:
@@ -326,7 +326,7 @@ class MboardRegsControl(object):
         Get GPS status
         """
         mask = 0x1F
-        with self.regs.open():
+        with self.regs:
             gps_status = self.peek32(self.MB_GPS_STATUS) & mask
         return gps_status
 
@@ -339,7 +339,7 @@ class MboardRegsControl(object):
             "Enabling" if enable else "Disabling"
         ))
         mask = 0xFFFFFFFF ^ (0b1 << self.MB_GPS_CTRL_PWR_EN)
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_GPS_CTRL) & mask
             reg_val = reg_val | (enable << self.MB_GPS_CTRL_PWR_EN)
             self.log.trace("Writing MB_GPS_CTRL to 0x{:08X}".format(reg_val))
@@ -350,7 +350,7 @@ class MboardRegsControl(object):
         Check the status of the reference clock (adf4002) in FPGA.
         """
         mask = 0b1 << self.MB_CLOCK_CTRL_REF_CLK_LOCKED
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_CLOCK_CTRL)
         locked = (reg_val & mask) > 0
         if not locked:
@@ -366,7 +366,7 @@ class MboardRegsControl(object):
         channel mode = "MIMO" for mimo
         channel mode = "SISO_TX1", "SISO_TX0" for siso tx1, tx0 respectively.
         """
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_DBOARD_CTRL)
             if channel_mode == "MIMO":
                 reg_val = (0b1 << self.MB_DBOARD_CTRL_MIMO)
@@ -390,7 +390,7 @@ class MboardRegsControl(object):
         Check the status of TX LO lock from CTRL_OUT pins from Catalina
         """
         mask = 0b1 << self.MB_DBOARD_STATUS_TX_LOCK
-        with self.regs.open():
+        with self.regs:
             reg_val =  self.peek32(self.MB_DBOARD_STATUS)
         locked = (reg_val & mask) > 0
         if not locked:
@@ -404,7 +404,7 @@ class MboardRegsControl(object):
         Check the status of RX LO lock from CTRL_OUT pins from Catalina
         """
         mask = 0b1 << self.MB_DBOARD_STATUS_RX_LOCK
-        with self.regs.open():
+        with self.regs:
             reg_val =  self.peek32(self.MB_DBOARD_STATUS)
         locked = (reg_val & mask) > 0
         if not locked:
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
index 756f0f788..009eb123b 100644
--- a/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
+++ b/mpm/python/usrp_mpm/periph_manager/n3xx_periphs.py
@@ -204,7 +204,7 @@ class MboardRegsControl(object):
         The return is a tuple of
         2 numbers: (major compat number, minor compat number )
         """
-        with self.regs.open():
+        with self.regs:
             compat_number = self.peek32(self.M_COMPAT_NUM)
         minor = compat_number & 0xff
         major = (compat_number>>16) & 0xff
@@ -215,7 +215,7 @@ class MboardRegsControl(object):
         Arguments:
             value {unsigned} -- value is a single bit bit mask of 12 pins GPIO
         """
-        with self.regs.open():
+        with self.regs:
             return self.poke32(self.MB_GPIO_MASTER, value)
 
     def get_fp_gpio_master(self):
@@ -224,7 +224,7 @@ class MboardRegsControl(object):
            0: means the pin is driven by PL
            1: means the pin is driven by PS
         """
-        with self.regs.open():
+        with self.regs:
             return self.peek32(self.MB_GPIO_MASTER) & 0xfff
 
     def set_fp_gpio_radio_src(self, value):
@@ -236,7 +236,7 @@ class MboardRegsControl(object):
            10: means the pin is driven by radio 2
            11: means the pin is driven by radio 3
         """
-        with self.regs.open():
+        with self.regs:
             return self.poke32(self.MB_GPIO_RADIO_SRC, value)
 
     def get_fp_gpio_radio_src(self):
@@ -247,7 +247,7 @@ class MboardRegsControl(object):
            10: means the pin is driven by radio 2
            11: means the pin is driven by radio 3
         """
-        with self.regs.open():
+        with self.regs:
             return self.peek32(self.MB_GPIO_RADIO_SRC) & 0xffffff
 
     def get_build_timestamp(self):
@@ -256,7 +256,7 @@ class MboardRegsControl(object):
         The return is datetime string with the  ISO 8601 format
         (YYYY-MM-DD HH:MM:SS.mmmmmm)
         """
-        with self.regs.open():
+        with self.regs:
             datestamp_rb = self.peek32(self.MB_DATESTAMP)
         if datestamp_rb > 0:
             dt_str = datetime.datetime(
@@ -278,7 +278,7 @@ class MboardRegsControl(object):
         The return is a tuple of
         2 numbers: (short git hash, bool: is the tree dirty?)
         """
-        with self.regs.open():
+        with self.regs:
             git_hash_rb = self.peek32(self.MB_GIT_HASH)
         git_hash = git_hash_rb & 0x0FFFFFFF
         tree_dirty = ((git_hash_rb & 0xF0000000) > 0)
@@ -317,7 +317,7 @@ class MboardRegsControl(object):
         else:
             assert False
 
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_CLOCK_CTRL) & 0xFFFFFF90
             # prevent glitches by writing a cleared value first, then the final value.
             self.poke32(self.MB_CLOCK_CTRL, reg_val)
@@ -332,7 +332,7 @@ class MboardRegsControl(object):
         self.log.trace("%s PPS/Trig output!",
                        "Enabling" if enable else "Disabling")
         mask = 0xFFFFFFFF ^ (0b1 << self.MB_CLOCK_CTRL_PPS_OUT_EN)
-        with self.regs.open():
+        with self.regs:
             # mask the bit to clear it:
             reg_val = self.peek32(self.MB_CLOCK_CTRL) & mask
             if enable:
@@ -348,7 +348,7 @@ class MboardRegsControl(object):
         self.log.trace("%s measurement clock MMCM reset...",
                        "Asserting" if reset else "Clearing")
         mask = 0xFFFFFFFF ^ (0b1 << self.MB_CLOCK_CTRL_MEAS_CLK_RESET)
-        with self.regs.open():
+        with self.regs:
             # mask the bit to clear it
             reg_val = self.peek32(self.MB_CLOCK_CTRL) & mask
             if reset:
@@ -362,7 +362,7 @@ class MboardRegsControl(object):
         Check the status of the MMCM for the measurement clock in the FPGA TDC.
         """
         mask = 0b1 << self.MB_CLOCK_CTRL_MEAS_CLK_LOCKED
-        with self.regs.open():
+        with self.regs:
             reg_val = self.peek32(self.MB_CLOCK_CTRL)
         locked = (reg_val & mask) > 0
         if not locked:
@@ -377,7 +377,7 @@ class MboardRegsControl(object):
         Reads the type of the FPGA image currently loaded
         Returns a string with the type (ie HG, XG, AA, etc.)
         """
-        with self.regs.open():
+        with self.regs:
             sfp0_info_rb = self.peek32(self.MB_SFP0_INFO)
             sfp1_info_rb = self.peek32(self.MB_SFP1_INFO)
         # Print the registers values as 32-bit hex values
diff --git a/mpm/python/usrp_mpm/sys_utils/uio.py b/mpm/python/usrp_mpm/sys_utils/uio.py
index c99041492..c724557e6 100644
--- a/mpm/python/usrp_mpm/sys_utils/uio.py
+++ b/mpm/python/usrp_mpm/sys_utils/uio.py
@@ -23,9 +23,9 @@ def open_uio(label=None, path=None, length=None, read_only=True, offset=None):
     """Convenience function for creating a UIO object.
     Use this like you would open() for a file"""
     uio_obj = UIO(label, path, length, read_only, offset)
-    uio_obj.open()
+    uio_obj._open()
     yield uio_obj
-    uio_obj.close()
+    uio_obj._close()
 
 
 def get_all_uio_devs():
@@ -97,17 +97,24 @@ class UIO(object):
     - Use the instantiation of this class as a context manager (using a `with`
       statement), like this:
 
+    >>> uio0 = UIO(path="/dev/uio0"):
+    >>> with uio0:
+    >>>     uio0.peek32(addr)
+    >>>     uio0.poke32(addr, value)
+
+    Or like this:
+
     >>> with UIO(path="/dev/uio0") as uio0:
     >>>     uio0.peek32(addr)
     >>>     uio0.poke32(addr, value)
 
-    - Manually call open() and close():
+    - This is Highly Discouraged, but if you need to, manually call _open() and _close():
 
     >>> uio0 = UIO(path="/dev/uio0")
-    >>> uio0.open()
+    >>> uio0._open()
     >>> uio0.peek32(addr)
     >>> uio0.poke32(addr, value)
-    >>> uio0.close()
+    >>> uio0._close()
 
     Arguments:
     label -- Label of the UIO device. The label is set in the device tree
@@ -135,10 +142,12 @@ class UIO(object):
         else:
             self.log.trace("Using UIO device by label `{0}'".format(label))
             self._path, map_info = find_uio_device(label, self.log)
-        offset = offset or map_info['offset'] # If we ever support multiple maps, check if this is correct...
+        # TODO If we ever support multiple maps, check if this is correct...
+        offset = offset or map_info['offset']
         assert offset == 0 # ...and then remove this line
         length = length or map_info['size']
-        self.log.trace("UIO device is being opened read-{0}.".format("only" if read_only else "write"))
+        self.log.trace("UIO device is being opened read-{0}.".format(
+            "only" if read_only else "write"))
         if self._path is None:
             self.log.error("Could not find a UIO device for label {0}".format(label))
             raise RuntimeError("Could not find a UIO device for label {0}".format(label))
@@ -150,13 +159,13 @@ class UIO(object):
         self._ref_count = 0
 
     def __enter__(self):
-        return self.open()
+        return self._open()
 
     def __exit__(self, exc_type, exc_value, traceback):
-        self.close()
+        self._close()
         return exc_type is None
 
-    def open(self):
+    def _open(self):
         """Actually open the UIO device.
 
         You need to call this before doing peeks and pokes. See also close().
@@ -169,7 +178,7 @@ class UIO(object):
         self._ref_count += 1
         return self
 
-    def close(self):
+    def _close(self):
         """Close a UIO device.
 
         UIO devices can be problematic with regards to file descriptor leakage,