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| author | Samuel O'Brien <sam.obrien@ni.com> | 2020-08-05 09:29:41 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-10-08 07:44:12 -0500 |
| commit | 267365c9458690842da549a00b7adb7946a1117d (patch) | |
| tree | 766067b75378f9fe9ee86cd3af20282fa94ef2bd /mpm/python/usrp_mpm/periph_manager/sim.py | |
| parent | ee9085a494d6f5030e49f5a47aff6a84008e0852 (diff) | |
| download | uhd-267365c9458690842da549a00b7adb7946a1117d.tar.gz uhd-267365c9458690842da549a00b7adb7946a1117d.tar.bz2 uhd-267365c9458690842da549a00b7adb7946a1117d.zip | |
sim: Clarify Naming of Streams
ChdrSniffer is renamed to ChdrEndpoint to clarify its function as the
actual destination of chdr packets, rather than just an observer.
TxWorker has been renamed to OutputStream and RxWorker has been renamed
to InputStream to avoid ambiguities regarding Tx and Rx terminology.
Signed-off-by: Samuel O'Brien <sam.obrien@ni.com>
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/sim.py')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/sim.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/sim.py b/mpm/python/usrp_mpm/periph_manager/sim.py index 7f9a610a7..20d2486c0 100644 --- a/mpm/python/usrp_mpm/periph_manager/sim.py +++ b/mpm/python/usrp_mpm/periph_manager/sim.py @@ -16,7 +16,7 @@ from usrp_mpm.mpmlog import get_logger from usrp_mpm.rpc_server import no_claim from usrp_mpm.periph_manager import PeriphManagerBase from usrp_mpm.simulator.sim_dboard_catalina import SimulatedCatalinaDboard -from usrp_mpm.simulator.chdr_sniffer import ChdrSniffer +from usrp_mpm.simulator.chdr_endpoint import ChdrEndpoint CLOCK_SOURCE_INTERNAL = "internal" @@ -83,7 +83,7 @@ class sim(PeriphManagerBase): super().__init__() self.device_id = 1 - self.chdr_sniffer = ChdrSniffer(self.log, args) + self.chdr_endpoint = ChdrEndpoint(self.log, args) # Unlike the real hardware drivers, if there is an exception here, # we just crash. No use missing an error when testing. |