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author | Martin Braun <martin.braun@ettus.com> | 2017-05-03 18:40:31 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:03:53 -0800 |
commit | b5b1ef2de2d554f16f67e254335265186fb642fa (patch) | |
tree | 64fe6e7660e63a32100576a7b90819b936403517 /mpm/python/usrp_mpm/periph_manager/n310.py | |
parent | 6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad (diff) | |
download | uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.tar.gz uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.tar.bz2 uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.zip |
mpm: Various EISCAT fixes
Diffstat (limited to 'mpm/python/usrp_mpm/periph_manager/n310.py')
-rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 1bf204218..97157ad1b 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -256,4 +256,5 @@ class n310(PeriphManagerBase): self.log.trace( "Updating reference clock on dboard `{}' to {} MHz...".format(slot, ref_clk_freq/1e6) ) + dboard.update_ref_clock_freq(ref_clk_freq) |