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| author | Martin Braun <martin.braun@ettus.com> | 2017-05-03 18:40:31 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:03:53 -0800 |
| commit | b5b1ef2de2d554f16f67e254335265186fb642fa (patch) | |
| tree | 64fe6e7660e63a32100576a7b90819b936403517 /mpm/python | |
| parent | 6a2a8bb2f7c7a58c39e83776c1b9fe6692b922ad (diff) | |
| download | uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.tar.gz uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.tar.bz2 uhd-b5b1ef2de2d554f16f67e254335265186fb642fa.zip | |
mpm: Various EISCAT fixes
Diffstat (limited to 'mpm/python')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py | 1 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/base.py | 2 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n310.py | 1 |
4 files changed, 4 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/CMakeLists.txt b/mpm/python/usrp_mpm/dboard_manager/CMakeLists.txt index 9cd65fa08..978e45ead 100644 --- a/mpm/python/usrp_mpm/dboard_manager/CMakeLists.txt +++ b/mpm/python/usrp_mpm/dboard_manager/CMakeLists.txt @@ -25,6 +25,7 @@ SET(USRP_MPM_DBMGR_FILES ${CMAKE_CURRENT_SOURCE_DIR}/test.py ${CMAKE_CURRENT_SOURCE_DIR}/magnesium.py ${CMAKE_CURRENT_SOURCE_DIR}/eiscat.py + ${CMAKE_CURRENT_SOURCE_DIR}/lmk_eiscat.py ${CMAKE_CURRENT_SOURCE_DIR}/unknown.py ) LIST(APPEND USRP_MPM_FILES ${USRP_MPM_DBMGR_FILES}) diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py index f169e2589..ee4dd3e38 100644 --- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py @@ -30,6 +30,7 @@ class LMK04828EISCAT(object): def __init__(self, regs_iface, ref_clock_freq, slot=None): slot = slot or "-A" self.log = get_logger("LMK04828"+slot) + self.log.trace("Using reference clock frequency {} MHz".format(ref_clock_freq/1e6)) assert ref_clock_freq in (10e6, 20e6) self.ref_clock_freq = ref_clock_freq self.regs_iface = regs_iface diff --git a/mpm/python/usrp_mpm/periph_manager/base.py b/mpm/python/usrp_mpm/periph_manager/base.py index f65d9c780..ea2a145a8 100644 --- a/mpm/python/usrp_mpm/periph_manager/base.py +++ b/mpm/python/usrp_mpm/periph_manager/base.py @@ -74,7 +74,7 @@ class PeriphManagerBase(object): # eeprom_data = EEPROM().read_eeprom(get_eeprom_path(eeprom_addr)) eeprom_data = None # I know spidev masters on the dboard slots - hw_pid = 2 + hw_pid = 3 if hw_pid in dboard_manager.HW_PIDS: spi_devices = sorted(get_spidev_nodes("e0006000.spi")) self.log.debug("Found spidev nodes: {0}".format(spi_devices)) diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 1bf204218..97157ad1b 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -256,4 +256,5 @@ class n310(PeriphManagerBase): self.log.trace( "Updating reference clock on dboard `{}' to {} MHz...".format(slot, ref_clk_freq/1e6) ) + dboard.update_ref_clock_freq(ref_clk_freq) |