mpm: Implement 32 bit register interface with SPI

Implement SPI transfers which are 12 bytes in length to support
access for 32 bit register interfaces. 12 byte transactions are
necessary for Titanium MB PS CPLD SPI transactions. This implementation
supports 48 bits of TX data per transfer and offsets all flags and
data shifts from the end of the TX data portion of the transfer buffer
rather than the end of the entire transfer buffer.

5 files changed, 25 insertions, 6 deletions

diff --git a/mpm/include/mpm/spi/spi_iface.hpp b/mpm/include/mpm/spi/spi_iface.hpp
index e295d1bb7..39390f7e2 100644
--- a/mpm/include/mpm/spi/spi_iface.hpp
+++ b/mpm/include/mpm/spi/spi_iface.hpp
@@ -36,6 +36,14 @@ public:
      */
     virtual uint32_t transfer24_16(const uint32_t data) = 0;
 
+    /*! Convenience function: SPI xfer is 64 bits write, 40 bits read.
+     *
+     * \param data The write data for this xfer
+     *
+     * \return 40 bits worth of the return xfer
+     */
+    virtual uint64_t transfer64_40(const uint64_t data) = 0;
+
     /*!
      * \param device The path to the spidev used (e.g. "/dev/spidev0.0")
      * \param speed_hz Transaction speed in Hz
diff --git a/mpm/include/mpm/spi/spi_python.hpp b/mpm/include/mpm/spi/spi_python.hpp
index 464df8d8b..0cadcad53 100644
--- a/mpm/include/mpm/spi/spi_python.hpp
+++ b/mpm/include/mpm/spi/spi_python.hpp
@@ -18,5 +18,6 @@ void export_spi(py::module& top_module)
     m.def("make_spidev", &mpm::spi::spi_iface::make_spidev);
 
     py::class_<mpm::spi::spi_iface, std::shared_ptr<mpm::spi::spi_iface>>(m, "spi_iface")
-        .def("transfer24_8", &mpm::spi::spi_iface::transfer24_8);
+        .def("transfer24_8", &mpm::spi::spi_iface::transfer24_8)
+        .def("transfer64_40", &mpm::spi::spi_iface::transfer64_40);
 }
diff --git a/mpm/include/mpm/spi/spi_regs_iface.hpp b/mpm/include/mpm/spi/spi_regs_iface.hpp
index 6351cf9b5..c731946fe 100644
--- a/mpm/include/mpm/spi/spi_regs_iface.hpp
+++ b/mpm/include/mpm/spi/spi_regs_iface.hpp
@@ -14,8 +14,8 @@ namespace mpm { namespace spi {
 mpm::types::regs_iface::sptr make_spi_regs_iface(mpm::spi::spi_iface::sptr spi_iface,
     uint32_t addr_shift,
     uint32_t data_shift,
-    uint32_t read_flags,
-    uint32_t write_flags = 0);
+    uint64_t read_flags,
+    uint64_t write_flags = 0);
 
 /*! Convenience factory for regs_iface based on SPI based on spidev
  */
@@ -24,7 +24,7 @@ mpm::types::regs_iface::sptr make_spidev_regs_iface(const std::string& device,
     const int spi_mode,
     uint32_t addr_shift,
     uint32_t data_shift,
-    uint32_t read_flags,
-    uint32_t write_flags = 0);
+    uint64_t read_flags,
+    uint64_t write_flags = 0);
 
 }}; /* namespace mpm::spi */
diff --git a/mpm/include/mpm/types/regs_iface.hpp b/mpm/include/mpm/types/regs_iface.hpp
index b47c31821..97fdd232c 100644
--- a/mpm/include/mpm/types/regs_iface.hpp
+++ b/mpm/include/mpm/types/regs_iface.hpp
@@ -33,6 +33,14 @@ public:
     /*! Write a 16-bit value to a given address
      */
     virtual void poke16(const uint32_t addr, const uint16_t data) = 0;
+
+    /*! Return a 32-bit value from a given address
+     */
+    virtual uint32_t peek32(const uint64_t addr) = 0;
+
+    /*! Write a 32-bit value to a given address
+     */
+    virtual void poke32(const uint64_t addr, const uint32_t data) = 0;
 };
 
 }}; // namespace mpm::types
diff --git a/mpm/include/mpm/types/types_python.hpp b/mpm/include/mpm/types/types_python.hpp
index cb2af5c4b..1c4c1c3b5 100644
--- a/mpm/include/mpm/types/types_python.hpp
+++ b/mpm/include/mpm/types/types_python.hpp
@@ -25,7 +25,9 @@ void export_types(py::module& top_module)
         .def("peek8", &regs_iface::peek8)
         .def("poke8", &regs_iface::poke8)
         .def("peek16", &regs_iface::peek16)
-        .def("poke16", &regs_iface::poke16);
+        .def("poke16", &regs_iface::poke16)
+        .def("peek32", &regs_iface::peek32)
+        .def("poke32", &regs_iface::poke32);
 
     py::class_<log_buf, std::shared_ptr<log_buf>>(m, "log_buf")
         .def_static("make_singleton", &log_buf::make_singleton)