uhd: Add support for the USRP X410

Co-authored-by: Lars Amsel <lars.amsel@ni.com>
Co-authored-by: Michael Auchter <michael.auchter@ni.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Cristina Fuentes <cristina.fuentes-curiel@ni.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Virendra Kakade <virendra.kakade@ni.com>
Co-authored-by: Lane Kolbly <lane.kolbly@ni.com>
Co-authored-by: Max Köhler <max.koehler@ni.com>
Co-authored-by: Andrew Lynch <andrew.lynch@ni.com>
Co-authored-by: Grant Meyerhoff <grant.meyerhoff@ni.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Thomas Vogel <thomas.vogel@ni.com>

3 files changed, 97 insertions, 0 deletions

diff --git a/host/tests/devtest/CMakeLists.txt b/host/tests/devtest/CMakeLists.txt
index e6cef17fe..3f09620bf 100644
--- a/host/tests/devtest/CMakeLists.txt
+++ b/host/tests/devtest/CMakeLists.txt
@@ -50,5 +50,8 @@ endif(ENABLE_N300)
 if(ENABLE_E320)
     ADD_DEVTEST("e320" "e3xx" "E32x")
 endif(ENABLE_E320)
+if(ENABLE_X400)
+    ADD_DEVTEST("x4x0" "x4xx" "X4x0")
+endif(ENABLE_X400)
 # Formatting
 message(STATUS "")
diff --git a/host/tests/devtest/devtest_x4x0.py b/host/tests/devtest/devtest_x4x0.py
new file mode 100644
index 000000000..c0b8bf4aa
--- /dev/null
+++ b/host/tests/devtest/devtest_x4x0.py
@@ -0,0 +1,75 @@
+#
+# Copyright 2015 Ettus Research LLC
+# Copyright 2020 Ettus Research, a National Instruments Brand
+#
+# SPDX-License-Identifier: GPL-3.0-or-later
+#
+"""
+Run device tests for the x4x0 series.
+"""
+
+# pylint: disable=wrong-import-position
+# pylint: disable=unused-import
+from benchmark_rate_test import uhd_benchmark_rate_test
+uhd_benchmark_rate_test.tests = {
+    'mimo_slow': {
+        'duration': 1,
+        'direction': 'tx,rx',
+        'chan': '0,1',
+        'rate': 1e6,
+        'acceptable-underruns': 500,
+        'tx_buffer': (0.1*1e6)+32e6*8*1/32,  # 32 MB DRAM for each channel (32 bit OTW format),
+        'rx_buffer': 0.1*1e6,
+    },
+    'mimo_fast': {
+        'duration': 1,
+        'direction': 'tx,rx',
+        'chan': '0,1',
+        'rate': 4.096e6,
+        'acceptable-underruns': 500,
+        'tx_buffer': (0.1*12.288e6)+32e6*8*1/32,  # 32 MB DRAM for each channel (32 bit OTW format),
+        'rx_buffer': 0.1*12.288e6,
+    },
+    'siso_chan0_slow': {
+        'duration': 1,
+        'direction': 'tx,rx',
+        'chan': '0',
+        'rate': 1e6,
+        'acceptable-underruns': 10,
+        'tx_buffer': (0.1*1e6)+32e6*8*1/32,  # 32 MB DRAM for each channel (32 bit OTW format),
+        'rx_buffer': 0.1*1e6,
+    },
+    'siso_chan1_slow': {
+        'duration': 1,
+        'direction': 'tx,rx',
+        'chan': '1',
+        'rate': 1e6,
+        'acceptable-underruns': 10,
+        'tx_buffer': (0.1*1e6)+32e6*8*1/32,  # 32 MB DRAM for each channel (32 bit OTW format),
+        'rx_buffer': 0.1*1e6,
+    },
+}
+
+from tx_waveforms_test import uhd_tx_waveforms_test
+uhd_tx_waveforms_test.tests = {
+    'chan0': {
+        'chan': '0',
+    },
+    'chan1': {
+        'chan': '0',
+    },
+    'both_chans': {
+        'chan': '0,1',
+    },
+}
+
+from rx_samples_to_file_test import rx_samples_to_file_test
+from tx_bursts_test import uhd_tx_bursts_test
+from test_pps_test import uhd_test_pps_test
+
+# Enable these when GPIO API is enabled
+# from gpio_test import gpio_test
+# from bitbang_test import bitbang_test
+
+from list_sensors_test import list_sensors_test
+from python_api_test import uhd_python_api_test
diff --git a/host/tests/devtest/multi_usrp_test.py b/host/tests/devtest/multi_usrp_test.py
index b9add8381..943733ba9 100755
--- a/host/tests/devtest/multi_usrp_test.py
+++ b/host/tests/devtest/multi_usrp_test.py
@@ -754,6 +754,25 @@ def get_device_config(usrp_type, device_config_path=None):
                 'get_gpio_banks',
             ],
         }
+    if usrp_type == 'x410':
+        return {
+            'skip': [
+                # No AGC on ZBX
+                'set_rx_agc',
+                # No IQ imbalance on ZBX
+                'set_rx_iq_balance',
+                'set_tx_iq_balance',
+                # No DC offset on ZBX
+                'set_rx_dc_offset',
+                'set_tx_dc_offset',
+                # No LO source control on ZBX
+                'set_rx_lo_source',
+                'set_tx_lo_source',
+                'set_rx_lo_export_enabled',
+                'set_tx_lo_export_enabled',
+            ],
+            'clock_sources': ['internal', 'mboard'],
+        }
     return {}
 
 def dump_defaults(usrp_type):