usrp2: created new gpio core and used in dboard iface

3 files changed, 153 insertions, 0 deletions

diff --git a/host/lib/usrp/cores/CMakeLists.txt b/host/lib/usrp/cores/CMakeLists.txt
index 4476c9424..2aa8f6b99 100644
--- a/host/lib/usrp/cores/CMakeLists.txt
+++ b/host/lib/usrp/cores/CMakeLists.txt
@@ -22,6 +22,7 @@
 INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR})
 
 LIBUHD_APPEND_SOURCES(
+    ${CMAKE_CURRENT_SOURCE_DIR}/gpio_core_200.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_100.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/spi_core_100.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/time64_core_200.cpp
diff --git a/host/lib/usrp/cores/gpio_core_200.cpp b/host/lib/usrp/cores/gpio_core_200.cpp
new file mode 100644
index 000000000..8639b1851
--- /dev/null
+++ b/host/lib/usrp/cores/gpio_core_200.cpp
@@ -0,0 +1,100 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "gpio_core_200.hpp"
+#include <uhd/types/dict.hpp>
+
+#define REG_GPIO_IDLE          _base + 0
+#define REG_GPIO_RX_ONLY       _base + 4
+#define REG_GPIO_TX_ONLY       _base + 8
+#define REG_GPIO_BOTH          _base + 12
+#define REG_GPIO_DDR           _base + 16
+#define REG_GPIO_READ          _base + 0 //any address will readback
+
+using namespace uhd;
+using namespace usrp;
+
+class gpio_core_200_impl : public gpio_core_200{
+public:
+    gpio_core_200_impl(wb_iface::sptr iface, const size_t base):
+        _iface(iface), _base(base) { /* NOP */ }
+
+    void set_pin_ctrl(const unit_t unit, const boost::uint16_t value){
+        _pin_ctrl[unit] = value; //shadow
+        this->update(); //full update
+    }
+
+    void set_atr_reg(const unit_t unit, const atr_reg_t atr, const boost::uint16_t value){
+        _atr_regs[unit][atr] = value;  //shadow
+        this->update(); //full update
+    }
+
+    void set_gpio_ddr(const unit_t unit, const boost::uint16_t value){
+        _gpio_ddr[unit] = value; //shadow
+        _iface->poke32(REG_GPIO_DDR, //update the 32 bit register
+            (boost::uint32_t(_gpio_ddr[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) |
+            (boost::uint32_t(_gpio_ddr[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX))
+        );
+    }
+
+    void set_gpio_out(const unit_t unit, const boost::uint16_t value){
+        _gpio_out[unit] = value; //shadow
+        this->update(); //full update
+    }
+
+    boost::uint16_t read_gpio(const unit_t unit){
+        return boost::uint16_t(_iface->peek32(REG_GPIO_READ) >> unit2shit(unit));
+    }
+
+private:
+    wb_iface::sptr _iface;
+    const size_t _base;
+
+    uhd::dict<unit_t, boost::uint16_t> _pin_ctrl, _gpio_out, _gpio_ddr;
+    uhd::dict<unit_t, uhd::dict<atr_reg_t, boost::uint16_t> > _atr_regs;
+
+    unsigned unit2shit(const unit_t unit){
+        return (unit == dboard_iface::UNIT_RX)? 0 : 16;
+    }
+
+    void update(void){
+        this->update(dboard_iface::ATR_REG_IDLE, REG_GPIO_IDLE);
+        this->update(dboard_iface::ATR_REG_TX_ONLY, REG_GPIO_TX_ONLY);
+        this->update(dboard_iface::ATR_REG_RX_ONLY, REG_GPIO_RX_ONLY);
+        this->update(dboard_iface::ATR_REG_FULL_DUPLEX, REG_GPIO_BOTH);
+    }
+
+    void update(const atr_reg_t atr, const size_t addr){
+        const boost::uint32_t atr_val =
+            (boost::uint32_t(_atr_regs[dboard_iface::UNIT_RX][atr]) << unit2shit(dboard_iface::UNIT_RX)) |
+            (boost::uint32_t(_atr_regs[dboard_iface::UNIT_TX][atr]) << unit2shit(dboard_iface::UNIT_TX));
+
+        const boost::uint32_t gpio_val =
+            (boost::uint32_t(_gpio_out[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) |
+            (boost::uint32_t(_gpio_out[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX));
+
+        const boost::uint32_t ctrl =
+            (boost::uint32_t(_pin_ctrl[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) |
+            (boost::uint32_t(_pin_ctrl[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX));
+        _iface->poke32(addr, (ctrl & atr_val) | ((~ctrl) & gpio_val));
+    }
+
+};
+
+gpio_core_200::sptr gpio_core_200::make(wb_iface::sptr iface, const size_t base){
+    return sptr(new gpio_core_200_impl(iface, base));
+}
diff --git a/host/lib/usrp/cores/gpio_core_200.hpp b/host/lib/usrp/cores/gpio_core_200.hpp
new file mode 100644
index 000000000..7ff2af649
--- /dev/null
+++ b/host/lib/usrp/cores/gpio_core_200.hpp
@@ -0,0 +1,52 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#ifndef INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP
+#define INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP
+
+#include <uhd/config.hpp>
+#include <uhd/usrp/dboard_iface.hpp>
+#include <boost/cstdint.hpp>
+#include <boost/utility.hpp>
+#include <boost/shared_ptr.hpp>
+#include "wb_iface.hpp"
+
+class gpio_core_200 : boost::noncopyable{
+public:
+    typedef boost::shared_ptr<gpio_core_200> sptr;
+
+    typedef uhd::usrp::dboard_iface::unit_t unit_t;
+    typedef uhd::usrp::dboard_iface::atr_reg_t atr_reg_t;
+
+    //! makes a new GPIO core from iface and slave base
+    static sptr make(wb_iface::sptr iface, const size_t base);
+
+    //! 1 = ATR
+    virtual void set_pin_ctrl(const unit_t unit, const boost::uint16_t value) = 0;
+
+    virtual void set_atr_reg(const unit_t unit, const atr_reg_t atr, const boost::uint16_t value) = 0;
+
+    //! 1 = OUTPUT
+    virtual void set_gpio_ddr(const unit_t unit, const boost::uint16_t value) = 0;
+
+    virtual void set_gpio_out(const unit_t unit, const boost::uint16_t value) = 0;
+
+    virtual boost::uint16_t read_gpio(const unit_t unit) = 0;
+
+};
+
+#endif /* INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP */