diff options
| -rw-r--r-- | host/lib/usrp/cores/CMakeLists.txt | 1 | ||||
| -rw-r--r-- | host/lib/usrp/cores/gpio_core_200.cpp | 100 | ||||
| -rw-r--r-- | host/lib/usrp/cores/gpio_core_200.hpp | 52 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/dboard_iface.cpp | 75 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_impl.cpp | 10 | ||||
| -rw-r--r-- | host/lib/usrp/usrp2/usrp2_regs.hpp | 26 |
6 files changed, 173 insertions, 91 deletions
diff --git a/host/lib/usrp/cores/CMakeLists.txt b/host/lib/usrp/cores/CMakeLists.txt index 4476c9424..2aa8f6b99 100644 --- a/host/lib/usrp/cores/CMakeLists.txt +++ b/host/lib/usrp/cores/CMakeLists.txt @@ -22,6 +22,7 @@ INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}) LIBUHD_APPEND_SOURCES( + ${CMAKE_CURRENT_SOURCE_DIR}/gpio_core_200.cpp ${CMAKE_CURRENT_SOURCE_DIR}/i2c_core_100.cpp ${CMAKE_CURRENT_SOURCE_DIR}/spi_core_100.cpp ${CMAKE_CURRENT_SOURCE_DIR}/time64_core_200.cpp diff --git a/host/lib/usrp/cores/gpio_core_200.cpp b/host/lib/usrp/cores/gpio_core_200.cpp new file mode 100644 index 000000000..8639b1851 --- /dev/null +++ b/host/lib/usrp/cores/gpio_core_200.cpp @@ -0,0 +1,100 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#include "gpio_core_200.hpp" +#include <uhd/types/dict.hpp> + +#define REG_GPIO_IDLE _base + 0 +#define REG_GPIO_RX_ONLY _base + 4 +#define REG_GPIO_TX_ONLY _base + 8 +#define REG_GPIO_BOTH _base + 12 +#define REG_GPIO_DDR _base + 16 +#define REG_GPIO_READ _base + 0 //any address will readback + +using namespace uhd; +using namespace usrp; + +class gpio_core_200_impl : public gpio_core_200{ +public: + gpio_core_200_impl(wb_iface::sptr iface, const size_t base): + _iface(iface), _base(base) { /* NOP */ } + + void set_pin_ctrl(const unit_t unit, const boost::uint16_t value){ + _pin_ctrl[unit] = value; //shadow + this->update(); //full update + } + + void set_atr_reg(const unit_t unit, const atr_reg_t atr, const boost::uint16_t value){ + _atr_regs[unit][atr] = value; //shadow + this->update(); //full update + } + + void set_gpio_ddr(const unit_t unit, const boost::uint16_t value){ + _gpio_ddr[unit] = value; //shadow + _iface->poke32(REG_GPIO_DDR, //update the 32 bit register + (boost::uint32_t(_gpio_ddr[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) | + (boost::uint32_t(_gpio_ddr[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX)) + ); + } + + void set_gpio_out(const unit_t unit, const boost::uint16_t value){ + _gpio_out[unit] = value; //shadow + this->update(); //full update + } + + boost::uint16_t read_gpio(const unit_t unit){ + return boost::uint16_t(_iface->peek32(REG_GPIO_READ) >> unit2shit(unit)); + } + +private: + wb_iface::sptr _iface; + const size_t _base; + + uhd::dict<unit_t, boost::uint16_t> _pin_ctrl, _gpio_out, _gpio_ddr; + uhd::dict<unit_t, uhd::dict<atr_reg_t, boost::uint16_t> > _atr_regs; + + unsigned unit2shit(const unit_t unit){ + return (unit == dboard_iface::UNIT_RX)? 0 : 16; + } + + void update(void){ + this->update(dboard_iface::ATR_REG_IDLE, REG_GPIO_IDLE); + this->update(dboard_iface::ATR_REG_TX_ONLY, REG_GPIO_TX_ONLY); + this->update(dboard_iface::ATR_REG_RX_ONLY, REG_GPIO_RX_ONLY); + this->update(dboard_iface::ATR_REG_FULL_DUPLEX, REG_GPIO_BOTH); + } + + void update(const atr_reg_t atr, const size_t addr){ + const boost::uint32_t atr_val = + (boost::uint32_t(_atr_regs[dboard_iface::UNIT_RX][atr]) << unit2shit(dboard_iface::UNIT_RX)) | + (boost::uint32_t(_atr_regs[dboard_iface::UNIT_TX][atr]) << unit2shit(dboard_iface::UNIT_TX)); + + const boost::uint32_t gpio_val = + (boost::uint32_t(_gpio_out[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) | + (boost::uint32_t(_gpio_out[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX)); + + const boost::uint32_t ctrl = + (boost::uint32_t(_pin_ctrl[dboard_iface::UNIT_RX]) << unit2shit(dboard_iface::UNIT_RX)) | + (boost::uint32_t(_pin_ctrl[dboard_iface::UNIT_TX]) << unit2shit(dboard_iface::UNIT_TX)); + _iface->poke32(addr, (ctrl & atr_val) | ((~ctrl) & gpio_val)); + } + +}; + +gpio_core_200::sptr gpio_core_200::make(wb_iface::sptr iface, const size_t base){ + return sptr(new gpio_core_200_impl(iface, base)); +} diff --git a/host/lib/usrp/cores/gpio_core_200.hpp b/host/lib/usrp/cores/gpio_core_200.hpp new file mode 100644 index 000000000..7ff2af649 --- /dev/null +++ b/host/lib/usrp/cores/gpio_core_200.hpp @@ -0,0 +1,52 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +#ifndef INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP +#define INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP + +#include <uhd/config.hpp> +#include <uhd/usrp/dboard_iface.hpp> +#include <boost/cstdint.hpp> +#include <boost/utility.hpp> +#include <boost/shared_ptr.hpp> +#include "wb_iface.hpp" + +class gpio_core_200 : boost::noncopyable{ +public: + typedef boost::shared_ptr<gpio_core_200> sptr; + + typedef uhd::usrp::dboard_iface::unit_t unit_t; + typedef uhd::usrp::dboard_iface::atr_reg_t atr_reg_t; + + //! makes a new GPIO core from iface and slave base + static sptr make(wb_iface::sptr iface, const size_t base); + + //! 1 = ATR + virtual void set_pin_ctrl(const unit_t unit, const boost::uint16_t value) = 0; + + virtual void set_atr_reg(const unit_t unit, const atr_reg_t atr, const boost::uint16_t value) = 0; + + //! 1 = OUTPUT + virtual void set_gpio_ddr(const unit_t unit, const boost::uint16_t value) = 0; + + virtual void set_gpio_out(const unit_t unit, const boost::uint16_t value) = 0; + + virtual boost::uint16_t read_gpio(const unit_t unit) = 0; + +}; + +#endif /* INCLUDED_LIBUHD_USRP_GPIO_CORE_200_HPP */ diff --git a/host/lib/usrp/usrp2/dboard_iface.cpp b/host/lib/usrp/usrp2/dboard_iface.cpp index 4ce49b409..c31fc52b7 100644 --- a/host/lib/usrp/usrp2/dboard_iface.cpp +++ b/host/lib/usrp/usrp2/dboard_iface.cpp @@ -15,6 +15,7 @@ // along with this program. If not, see <http://www.gnu.org/licenses/>. // +#include "gpio_core_200.hpp" #include "usrp2_iface.hpp" #include "clock_ctrl.hpp" #include "usrp2_regs.hpp" //wishbone address constants @@ -80,8 +81,7 @@ public: private: usrp2_iface::sptr _iface; usrp2_clock_ctrl::sptr _clock_ctrl; - boost::uint32_t _ddr_shadow; - boost::uint32_t _gpio_shadow; + gpio_core_200::sptr _gpio; uhd::dict<unit_t, ad5623_regs_t> _dac_regs; uhd::dict<unit_t, double> _clock_rates; @@ -107,8 +107,7 @@ usrp2_dboard_iface::usrp2_dboard_iface( ){ _iface = iface; _clock_ctrl = clock_ctrl; - _ddr_shadow = 0; - _gpio_shadow = 0; + _gpio = gpio_core_200::make(_iface, GPIO_BASE); //reset the aux dacs _dac_regs[UNIT_RX] = ad5623_regs_t(); @@ -165,82 +164,28 @@ double usrp2_dboard_iface::get_codec_rate(unit_t){ /*********************************************************************** * GPIO **********************************************************************/ -static const uhd::dict<dboard_iface::unit_t, int> unit_to_shift = map_list_of - (dboard_iface::UNIT_RX, 0) - (dboard_iface::UNIT_TX, 16) -; - void usrp2_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){ - //calculate the new selection mux setting - boost::uint32_t new_sels = 0x0; - for(size_t i = 0; i < 16; i++){ - bool is_bit_set = (value & (0x1 << i)) != 0; - new_sels |= ((is_bit_set)? U2_FLAG_GPIO_SEL_ATR : U2_FLAG_GPIO_SEL_GPIO) << (i*2); - } - - //write the selection mux value to register - switch(unit){ - case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; - case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; - } + return _gpio->set_pin_ctrl(unit, value); } void usrp2_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){ - _ddr_shadow = \ - (_ddr_shadow & ~(0xffff << unit_to_shift[unit])) | - (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(U2_REG_GPIO_DDR, _ddr_shadow); + return _gpio->set_gpio_ddr(unit, value); } void usrp2_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){ - _gpio_shadow = \ - (_gpio_shadow & ~(0xffff << unit_to_shift[unit])) | - (boost::uint32_t(value) << unit_to_shift[unit]); - _iface->poke32(U2_REG_GPIO_IO, _gpio_shadow); + return _gpio->set_gpio_out(unit, value); } boost::uint16_t usrp2_dboard_iface::read_gpio(unit_t unit){ - return boost::uint16_t(_iface->peek32(U2_REG_GPIO_IO) >> unit_to_shift[unit]); + return _gpio->read_gpio(unit); } void usrp2_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uint16_t value){ - //define mapping of unit to atr regs to register address - static const uhd::dict< - unit_t, uhd::dict<atr_reg_t, boost::uint32_t> - > unit_to_atr_to_addr = map_list_of - (UNIT_RX, map_list_of - (ATR_REG_IDLE, U2_REG_ATR_IDLE_RXSIDE) - (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_RXSIDE) - (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_RXSIDE) - (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_RXSIDE) - ) - (UNIT_TX, map_list_of - (ATR_REG_IDLE, U2_REG_ATR_IDLE_TXSIDE) - (ATR_REG_TX_ONLY, U2_REG_ATR_INTX_TXSIDE) - (ATR_REG_RX_ONLY, U2_REG_ATR_INRX_TXSIDE) - (ATR_REG_FULL_DUPLEX, U2_REG_ATR_FULL_TXSIDE) - ) - ; - _iface->poke16(unit_to_atr_to_addr[unit][atr], value); + return _gpio->set_atr_reg(unit, atr, value); } -void usrp2_dboard_iface::set_gpio_debug(unit_t unit, int which){ - this->set_gpio_ddr(unit, 0xffff); //all outputs - - //calculate the new selection mux setting - boost::uint32_t new_sels = 0x0; - int sel = (which == 0)? - U2_FLAG_GPIO_SEL_DEBUG_0: - U2_FLAG_GPIO_SEL_DEBUG_1; - for(size_t i = 0; i < 16; i++){ - new_sels |= sel << (i*2); - } - - //write the selection mux value to register - switch(unit){ - case UNIT_RX: _iface->poke32(U2_REG_GPIO_RX_SEL, new_sels); return; - case UNIT_TX: _iface->poke32(U2_REG_GPIO_TX_SEL, new_sels); return; - } +void usrp2_dboard_iface::set_gpio_debug(unit_t, int){ + throw uhd::not_implemented_error("no set_gpio_debug implemented"); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp index f87eb067e..8cf96721e 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.cpp +++ b/host/lib/usrp/usrp2/usrp2_impl.cpp @@ -356,6 +356,16 @@ usrp2_impl::usrp2_impl(const device_addr_t &_device_addr){ } _tree->create<std::string>(mb_path / "fpga_version").set(str(boost::format("%u.%u") % fpga_major % fpga_minor)); + //-------------------------------------------------------------- + if (fpga_minor == 0){ //!!! special temporary check !!!// + UHD_MSG(warning) + << "Detected FPGA pre-release minor version 0.\n" + << "This build has known transmit issues.\n" + << "Please grab the latest images from the wiki.\n" + ; + } + //-------------------------------------------------------------- + //lock the device/motherboard to this process _mbc[mb].iface->lock_device(true); diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 555e4a3e7..8839997f1 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -102,30 +102,4 @@ #define U2_REG_TIME64_SECS_RB_PPS READBACK_BASE + 4*14 #define U2_REG_TIME64_TICKS_RB_PPS READBACK_BASE + 4*15 -//////////////////////////////////////////////// -// GPIO -//////////////////////////////////////////////// -#define U2_REG_GPIO_IO GPIO_BASE + 0 -#define U2_REG_GPIO_DDR GPIO_BASE + 4 -#define U2_REG_GPIO_TX_SEL GPIO_BASE + 8 -#define U2_REG_GPIO_RX_SEL GPIO_BASE + 12 - -// each 2-bit sel field is layed out this way -#define U2_FLAG_GPIO_SEL_GPIO 0 // if pin is an output, set by GPIO register -#define U2_FLAG_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define U2_FLAG_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define U2_FLAG_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric - -/////////////////////////////////////////////////// -// ATR Controller -//////////////////////////////////////////////// -#define U2_REG_ATR_IDLE_TXSIDE ATR_BASE + 0 -#define U2_REG_ATR_IDLE_RXSIDE ATR_BASE + 2 -#define U2_REG_ATR_INTX_TXSIDE ATR_BASE + 4 -#define U2_REG_ATR_INTX_RXSIDE ATR_BASE + 6 -#define U2_REG_ATR_INRX_TXSIDE ATR_BASE + 8 -#define U2_REG_ATR_INRX_RXSIDE ATR_BASE + 10 -#define U2_REG_ATR_FULL_TXSIDE ATR_BASE + 12 -#define U2_REG_ATR_FULL_RXSIDE ATR_BASE + 14 - #endif /* INCLUDED_USRP2_REGS_HPP */ |