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author | Nick Foster <nick@nerdnetworks.org> | 2010-08-10 17:02:47 -0700 |
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committer | Nick Foster <nick@nerdnetworks.org> | 2010-08-10 17:02:47 -0700 |
commit | 663808e847c4970551c6c8127c2c5d816e2a2014 (patch) | |
tree | 12183a2d7ea5434880dccfa414d8a378ae134abc /host/lib/ic_reg_maps/common.py | |
parent | 90a5d84a18aaa338092e572ff257aab1fdcc8e6b (diff) | |
parent | 9e419c7b7f35062ceb2ed4e508cadb163067593f (diff) | |
download | uhd-663808e847c4970551c6c8127c2c5d816e2a2014.tar.gz uhd-663808e847c4970551c6c8127c2c5d816e2a2014.tar.bz2 uhd-663808e847c4970551c6c8127c2c5d816e2a2014.zip |
Merge branch 'master' into usrp2p
this was the merge from hell
Conflicts:
firmware/microblaze/Makefile.am
firmware/microblaze/bootstrap
firmware/microblaze/configure.ac
firmware/microblaze/lib/Makefile.inc
host/lib/CMakeLists.txt
host/lib/usrp/mimo_usrp.cpp
host/lib/usrp/simple_usrp.cpp
host/lib/usrp/usrp2/clock_ctrl.cpp
host/lib/usrp/usrp2/codec_impl.cpp
host/lib/usrp/usrp2/dboard_impl.cpp
host/lib/usrp/usrp2/mboard_impl.cpp
host/lib/usrp/usrp2/usrp2_iface.hpp
host/lib/usrp/usrp2/usrp2_impl.hpp
host/lib/usrp/usrp2/usrp2_regs.hpp
host/test/CMakeLists.txt
Diffstat (limited to 'host/lib/ic_reg_maps/common.py')
-rw-r--r-- | host/lib/ic_reg_maps/common.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/host/lib/ic_reg_maps/common.py b/host/lib/ic_reg_maps/common.py index 47325a7e3..986093004 100644 --- a/host/lib/ic_reg_maps/common.py +++ b/host/lib/ic_reg_maps/common.py @@ -173,7 +173,7 @@ class mreg: def get_type(self): return 'boost::uint%d_t'%max(2**math.ceil(math.log(self.get_bit_width(), 2)), 8) -def generate(name, regs_tmpl, body_tmpl='', file=__file__): +def generate(name, regs_tmpl, body_tmpl='', file=__file__, append=False): #evaluate the regs template and parse each line into a register regs = list(); mregs = list() for entry in parse_tmpl(regs_tmpl).splitlines(): @@ -193,4 +193,4 @@ def generate(name, regs_tmpl, body_tmpl='', file=__file__): ) #write the generated code to file specified by argv1 - open(sys.argv[1], 'w').write(code) + open(sys.argv[1], 'a' if append else 'w').write(code) |