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authorWade Fife <wade.fife@ettus.com>2020-04-06 16:12:10 -0500
committerWade Fife <wade.fife@ettus.com>2020-04-21 10:31:07 -0500
commit8db85296df1843ddd851cd5b237c443bbf3e30dd (patch)
treea77d53cc93951b7e789f1c34673b20b42d6aca03 /host/include
parent1a7f55f3bd1db83e2d9b2b2f3b0c2f8f5f5b60e3 (diff)
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utils: Add sideband_at_end support to Mako template
This adds a new option to the "AXI-Stream Data" (axis_data) FPGA interface type. The new option, "sideband_at_end", can be added to the output port of a block's YAML description to control whether the sideband information should be sampled at the end (sideband_at_end: 1) or the beginning (sideband_at_end: 0) of the AXI-Stream packet.
Diffstat (limited to 'host/include')
-rw-r--r--host/include/uhd/rfnoc/blocks/fosphor.yml2
1 files changed, 2 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/fosphor.yml b/host/include/uhd/rfnoc/blocks/fosphor.yml
index d803dc602..8890e1f90 100644
--- a/host/include/uhd/rfnoc/blocks/fosphor.yml
+++ b/host/include/uhd/rfnoc/blocks/fosphor.yml
@@ -41,6 +41,7 @@ data:
nipc: 4
info_fifo_depth: 32
payload_fifo_depth: 32
+ sideband_at_end: False
format: u8
mdata_sig: ~
wf:
@@ -48,6 +49,7 @@ data:
nipc: 4
info_fifo_depth: 32
payload_fifo_depth: 32
+ sideband_at_end: False
format: u8
mdata_sig: ~