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authorWade Fife <wade.fife@ettus.com>2020-04-06 16:12:10 -0500
committerWade Fife <wade.fife@ettus.com>2020-04-21 10:31:07 -0500
commit8db85296df1843ddd851cd5b237c443bbf3e30dd (patch)
treea77d53cc93951b7e789f1c34673b20b42d6aca03
parent1a7f55f3bd1db83e2d9b2b2f3b0c2f8f5f5b60e3 (diff)
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utils: Add sideband_at_end support to Mako template
This adds a new option to the "AXI-Stream Data" (axis_data) FPGA interface type. The new option, "sideband_at_end", can be added to the output port of a block's YAML description to control whether the sideband information should be sampled at the end (sideband_at_end: 1) or the beginning (sideband_at_end: 0) of the AXI-Stream packet.
-rw-r--r--host/include/uhd/rfnoc/blocks/fosphor.yml2
-rw-r--r--host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako1
-rw-r--r--host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako34
-rw-r--r--host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako2
4 files changed, 24 insertions, 15 deletions
diff --git a/host/include/uhd/rfnoc/blocks/fosphor.yml b/host/include/uhd/rfnoc/blocks/fosphor.yml
index d803dc602..8890e1f90 100644
--- a/host/include/uhd/rfnoc/blocks/fosphor.yml
+++ b/host/include/uhd/rfnoc/blocks/fosphor.yml
@@ -41,6 +41,7 @@ data:
nipc: 4
info_fifo_depth: 32
payload_fifo_depth: 32
+ sideband_at_end: False
format: u8
mdata_sig: ~
wf:
@@ -48,6 +49,7 @@ data:
nipc: 4
info_fifo_depth: 32
payload_fifo_depth: 32
+ sideband_at_end: False
format: u8
mdata_sig: ~
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
index 9d7fb75cb..16db14394 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
@@ -28,6 +28,7 @@
.s_${port_name}_axis_tready (s_${port_name}_axis_tready),
.s_${port_name}_axis_ttimestamp (s_${port_name}_axis_ttimestamp),
.s_${port_name}_axis_thas_time (s_${port_name}_axis_thas_time),
+ .s_${port_name}_axis_tlength (s_${port_name}_axis_tlength),
.s_${port_name}_axis_teov (s_${port_name}_axis_teov),
.s_${port_name}_axis_teob (s_${port_name}_axis_teob)${"," if (idx < num_outputs -1) else ""}
%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
index f2fa6e9da..95be68f2a 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
@@ -37,7 +37,7 @@ import math
.m_axis_tready (m_${port_name}_axis_tready[i]),
.m_axis_ttimestamp (m_${port_name}_axis_ttimestamp[64*i+:64]),
.m_axis_thas_time (m_${port_name}_axis_thas_time[i]),
- .m_axis_tlength (m_${port_name}_axis_tlength[i*16+:16]),
+ .m_axis_tlength (m_${port_name}_axis_tlength[16*i+:16]),
.m_axis_teov (m_${port_name}_axis_teov[i]),
.m_axis_teob (m_${port_name}_axis_teob[i]),
.flush_en (data_i_flush_en),
@@ -99,13 +99,14 @@ import math
%if num_ports != 1:
for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
axis_data_to_chdr #(
- .CHDR_W (CHDR_W),
- .ITEM_W (${port_info['item_width']}),
- .NIPC (${port_info['nipc']}),
- .SYNC_CLKS (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
- .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
- .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
- .MTU (MTU)
+ .CHDR_W (CHDR_W),
+ .ITEM_W (${port_info['item_width']}),
+ .NIPC (${port_info['nipc']}),
+ .SYNC_CLKS (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+ .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+ .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+ .MTU (MTU),
+ .SIDEBAND_AT_END (${int(port_info['sideband_at_end']) if 'sideband_at_end' in port_info else 1})
) axis_data_to_chdr_out_${port_name} (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
@@ -122,6 +123,7 @@ import math
.s_axis_tready (s_${port_name}_axis_tready[i]),
.s_axis_ttimestamp (s_${port_name}_axis_ttimestamp[64*i+:64]),
.s_axis_thas_time (s_${port_name}_axis_thas_time[i]),
+ .s_axis_tlength (s_${port_name}_axis_tlength[16*i+:16]),
.s_axis_teov (s_${port_name}_axis_teov[i]),
.s_axis_teob (s_${port_name}_axis_teob[i]),
.flush_en (data_o_flush_en),
@@ -132,13 +134,14 @@ import math
end
%else:
axis_data_to_chdr #(
- .CHDR_W (CHDR_W),
- .ITEM_W (${port_info['item_width']}),
- .NIPC (${port_info['nipc']}),
- .SYNC_CLKS (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
- .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
- .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
- .MTU (MTU)
+ .CHDR_W (CHDR_W),
+ .ITEM_W (${port_info['item_width']}),
+ .NIPC (${port_info['nipc']}),
+ .SYNC_CLKS (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+ .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+ .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+ .MTU (MTU),
+ .SIDEBAND_AT_END (${int(port_info['sideband_at_end']) if 'sideband_at_end' in port_info else 1})
) axis_data_to_chdr_out_${port_name} (
.axis_chdr_clk (rfnoc_chdr_clk),
.axis_chdr_rst (rfnoc_chdr_rst),
@@ -155,6 +158,7 @@ import math
.s_axis_tready (s_${port_name}_axis_tready),
.s_axis_ttimestamp (s_${port_name}_axis_ttimestamp),
.s_axis_thas_time (s_${port_name}_axis_thas_time),
+ .s_axis_tlength (s_${port_name}_axis_tlength),
.s_axis_teov (s_${port_name}_axis_teov),
.s_axis_teob (s_${port_name}_axis_teob),
.flush_en (data_o_flush_en),
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
index 9b33b84d1..dd12f06e8 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
@@ -61,6 +61,7 @@
${out_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_tready${term}
${in_wire}wire [${num_ports}*64-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term}
${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_thas_time${term}
+ ${in_wire}wire [${num_ports}*16-1:0] ${sl_pre}${port_name}_axis_tlength${term}
${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_teov${term}
${in_wire}wire [${num_ports}-1:0] ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) else ""}
%else:
@@ -72,6 +73,7 @@
${out_wire}wire ${sl_pre}${port_name}_axis_tready${term}
${in_wire}wire [63:0] ${sl_pre}${port_name}_axis_ttimestamp${term}
${in_wire}wire ${sl_pre}${port_name}_axis_thas_time${term}
+ ${in_wire}wire [15:0] ${sl_pre}${port_name}_axis_tlength${term}
${in_wire}wire ${sl_pre}${port_name}_axis_teov${term}
${in_wire}wire ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_outputs - 1) else ""}
%endif