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authorWade Fife <wade.fife@ettus.com>2021-10-27 10:57:16 -0500
committerWade Fife <wade.fife@ettus.com>2021-11-04 15:50:54 -0500
commitec814ff0c30cc3339c6e3d77862037158bca75ec (patch)
tree23920e956ed161cf81bd4e972d8047c00f9a7e54 /host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile
parenta99fec3973488e27eec1a06cb48a0725219b8c1b (diff)
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examples: Test all variants in gain testbench
Diffstat (limited to 'host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile')
-rw-r--r--host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile5
1 files changed, 3 insertions, 2 deletions
diff --git a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile
index 0239041b9..395698dc0 100644
--- a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile
+++ b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright 2019 Ettus Research, A National Instruments Brand
+# Copyright 2021 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
@@ -47,11 +47,12 @@ $(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
-SIM_TOP = rfnoc_block_gain_tb glbl
+SIM_TOP = rfnoc_block_gain_all_tb glbl
SIM_SRCS = \
$(abspath $(IP_BUILD_DIR)/cmplx_mul/sim/cmplx_mul.vhd) \
$(abspath $(IP_BUILD_DIR)/complex_multiplier/sim/complex_multiplier.vhd) \
$(abspath rfnoc_block_gain_tb.sv) \
+$(abspath rfnoc_block_gain_all_tb.sv) \
$(VIVADO_PATH)/data/verilog/src/glbl.v \
#-------------------------------------------------