From ec814ff0c30cc3339c6e3d77862037158bca75ec Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 27 Oct 2021 10:57:16 -0500 Subject: examples: Test all variants in gain testbench --- host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile') diff --git a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile index 0239041b9..395698dc0 100644 --- a/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile +++ b/host/examples/rfnoc-example/fpga/rfnoc_block_gain/Makefile @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Brand +# Copyright 2021 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # @@ -47,11 +47,12 @@ $(LIB_IP_COMPLEX_MULTIPLIER_SRCS) \ #------------------------------------------------- # Testbench Specific #------------------------------------------------- -SIM_TOP = rfnoc_block_gain_tb glbl +SIM_TOP = rfnoc_block_gain_all_tb glbl SIM_SRCS = \ $(abspath $(IP_BUILD_DIR)/cmplx_mul/sim/cmplx_mul.vhd) \ $(abspath $(IP_BUILD_DIR)/complex_multiplier/sim/complex_multiplier.vhd) \ $(abspath rfnoc_block_gain_tb.sv) \ +$(abspath rfnoc_block_gain_all_tb.sv) \ $(VIVADO_PATH)/data/verilog/src/glbl.v \ #------------------------------------------------- -- cgit v1.2.3