From b85b796cbc1f897a69ded1f3ecfba8ec92684c11 Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Thu, 10 Jun 2021 11:38:47 -0500
Subject: fpga: tools: Put SIM_SRCS at end of compile order

VHDL depends on the compile order. This commit changes the order so
that SIM_SRCS are compiled last with ModelSim to avoid issues with
dependencies.
---
 fpga/usrp3/tools/scripts/launch_vlint.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'fpga')

diff --git a/fpga/usrp3/tools/scripts/launch_vlint.sh b/fpga/usrp3/tools/scripts/launch_vlint.sh
index 43d64c786..c8d9b1d63 100755
--- a/fpga/usrp3/tools/scripts/launch_vlint.sh
+++ b/fpga/usrp3/tools/scripts/launch_vlint.sh
@@ -78,8 +78,8 @@ VHD_ARGS_FILE=vcomarglist.txt
 # Replace any directories with the sources they contain
 SOURCES=
 SOURCES+=$(replace_dirs_with_source $VLINT_INC_SRCS)
-SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS)
 SOURCES+=$(replace_dirs_with_source $VLINT_DESIGN_SRCS)
+SOURCES+=$(replace_dirs_with_source $VLINT_SIM_SRCS)
 
 # Separate the files by type and determine include directories to use
 V_FILES=
-- 
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