fpga: x400: Add SPI bus support for GPIO ports

2 files changed, 93 insertions, 0 deletions

diff --git a/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh
new file mode 100644
index 000000000..7ead185d7
--- /dev/null
+++ b/fpga/usrp3/top/x400/regmap/dig_ifc_regmap_utils.vh
@@ -0,0 +1,88 @@
+//
+// Copyright 2021 Ettus Research, A National Instruments Company
+//
+// SPDX-License-Identifier: LGPL-3.0-or-later
+//
+// Module: dig_ifc_regmap_utils.vh
+// Description:
+// The constants in this file are autogenerated by XmlParse.
+
+//===============================================================================
+// A numerically ordered list of registers and their HDL source files
+//===============================================================================
+
+  // SPI_SLAVE_CONFIG       : 0x0 (x4xx_gpio_spi.v)
+  // SPI_TRANSACTION_CONFIG : 0x10 (x4xx_gpio_spi.v)
+  // SPI_TRANSACTION_GO     : 0x14 (x4xx_gpio_spi.v)
+  // SPI_STATUS             : 0x18 (x4xx_gpio_spi.v)
+
+//===============================================================================
+// RegTypes
+//===============================================================================
+
+  // SPI_SETUP Type (from x4xx_gpio_spi.v)
+  localparam SPI_SETUP_SIZE = 32;
+  localparam SPI_SETUP_MASK = 32'hFFFFFFF;
+  localparam SLAVE_CLK_SIZE = 5;  //SPI_SETUP:SLAVE_CLK
+  localparam SLAVE_CLK_MSB  = 4;  //SPI_SETUP:SLAVE_CLK
+  localparam SLAVE_CLK      = 0;  //SPI_SETUP:SLAVE_CLK
+  localparam SLAVE_MOSI_SIZE = 5;  //SPI_SETUP:SLAVE_MOSI
+  localparam SLAVE_MOSI_MSB  = 9;  //SPI_SETUP:SLAVE_MOSI
+  localparam SLAVE_MOSI      = 5;  //SPI_SETUP:SLAVE_MOSI
+  localparam SLAVE_MISO_SIZE =  5;  //SPI_SETUP:SLAVE_MISO
+  localparam SLAVE_MISO_MSB  = 14;  //SPI_SETUP:SLAVE_MISO
+  localparam SLAVE_MISO      = 10;  //SPI_SETUP:SLAVE_MISO
+  localparam SLAVE_CS_SIZE =  5;  //SPI_SETUP:SLAVE_CS
+  localparam SLAVE_CS_MSB  = 19;  //SPI_SETUP:SLAVE_CS
+  localparam SLAVE_CS      = 15;  //SPI_SETUP:SLAVE_CS
+  localparam SPI_LENGTH_SIZE =  6;  //SPI_SETUP:SPI_LENGTH
+  localparam SPI_LENGTH_MSB  = 25;  //SPI_SETUP:SPI_LENGTH
+  localparam SPI_LENGTH      = 20;  //SPI_SETUP:SPI_LENGTH
+  localparam MISO_EDGE_SIZE =  1;  //SPI_SETUP:MISO_EDGE
+  localparam MISO_EDGE_MSB  = 26;  //SPI_SETUP:MISO_EDGE
+  localparam MISO_EDGE      = 26;  //SPI_SETUP:MISO_EDGE
+  localparam MOSI_EDGE_SIZE =  1;  //SPI_SETUP:MOSI_EDGE
+  localparam MOSI_EDGE_MSB  = 27;  //SPI_SETUP:MOSI_EDGE
+  localparam MOSI_EDGE      = 27;  //SPI_SETUP:MOSI_EDGE
+
+//===============================================================================
+// Register Group SPI_OVER_GPIO_REGS
+//===============================================================================
+
+  // SPI_SLAVE_CONFIG Register (from x4xx_gpio_spi.v)
+  localparam SPI_SLAVE_CONFIG_COUNT = 4; // Number of elements in array
+
+  // SPI_TRANSACTION_CONFIG Register (from x4xx_gpio_spi.v)
+  localparam SPI_TRANSACTION_CONFIG = 'h10; // Register Offset
+  localparam SPI_TRANSACTION_CONFIG_SIZE = 32;  // register width in bits
+  localparam SPI_TRANSACTION_CONFIG_MASK = 32'h3FFFF;
+  localparam SPI_CLK_DIV_SIZE = 16;  //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
+  localparam SPI_CLK_DIV_MSB  = 15;  //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
+  localparam SPI_CLK_DIV      =  0;  //SPI_TRANSACTION_CONFIG:SPI_CLK_DIV
+  localparam SPI_SLAVE_SELECT_SIZE =  2;  //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
+  localparam SPI_SLAVE_SELECT_MSB  = 17;  //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
+  localparam SPI_SLAVE_SELECT      = 16;  //SPI_TRANSACTION_CONFIG:SPI_SLAVE_SELECT
+
+  // SPI_TRANSACTION_GO Register (from x4xx_gpio_spi.v)
+  localparam SPI_TRANSACTION_GO = 'h14; // Register Offset
+  localparam SPI_TRANSACTION_GO_SIZE = 32;  // register width in bits
+  localparam SPI_TRANSACTION_GO_MASK = 32'hFFFFFFFF;
+  localparam SPI_DATA_SIZE = 32;  //SPI_TRANSACTION_GO:SPI_DATA
+  localparam SPI_DATA_MSB  = 31;  //SPI_TRANSACTION_GO:SPI_DATA
+  localparam SPI_DATA      =  0;  //SPI_TRANSACTION_GO:SPI_DATA
+
+  // SPI_STATUS Register (from x4xx_gpio_spi.v)
+  localparam SPI_STATUS = 'h18; // Register Offset
+  localparam SPI_STATUS_SIZE = 32;  // register width in bits
+  localparam SPI_STATUS_MASK = 32'h1FFFFFF;
+  localparam SPI_RESPONSE_SIZE = 24;  //SPI_STATUS:SPI_RESPONSE
+  localparam SPI_RESPONSE_MSB  = 23;  //SPI_STATUS:SPI_RESPONSE
+  localparam SPI_RESPONSE      =  0;  //SPI_STATUS:SPI_RESPONSE
+  localparam SPI_READY_SIZE =  1;  //SPI_STATUS:SPI_READY
+  localparam SPI_READY_MSB  = 24;  //SPI_STATUS:SPI_READY
+  localparam SPI_READY      = 24;  //SPI_STATUS:SPI_READY
+
+  // Return the offset of an element of register array SPI_SLAVE_CONFIG
+  function integer SPI_SLAVE_CONFIG (input integer i);
+    SPI_SLAVE_CONFIG = (i * 'h4) + 'h0;
+  endfunction
diff --git a/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh b/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh
index 62de3d75e..6916dc79c 100644
--- a/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh
+++ b/fpga/usrp3/top/x400/regmap/radio_dio_regmap_utils.vh
@@ -13,6 +13,7 @@
 
   // RADIO_GPIO_ATR_REGS : 0x0 (x4xx_core_common.v)
   // DIO_SOURCE_CONTROL  : 0x1000 (x4xx_core_common.v)
+  // DIGITAL_IFC_REGS    : 0x2000 (x4xx_core_common.v)
 
 //===============================================================================
 // RegTypes
@@ -29,3 +30,7 @@
   // DIO_SOURCE_CONTROL Window (from x4xx_core_common.v)
   localparam DIO_SOURCE_CONTROL = 'h1000; // Window Offset
   localparam DIO_SOURCE_CONTROL_SIZE = 'h1000;  // size in bytes
+
+  // DIGITAL_IFC_REGS Window (from x4xx_core_common.v)
+  localparam DIGITAL_IFC_REGS = 'h2000; // Window Offset
+  localparam DIGITAL_IFC_REGS_SIZE = 'h1000;  // size in bytes