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| author | Javier Valenzuela <javier.valenzuela@ni.com> | 2021-09-27 14:35:57 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-01-25 10:18:47 -0700 |
| commit | 4bfbb9eeec92fdd3e9d7096006f63477d4848f76 (patch) | |
| tree | 3e0351173fc281dad45ae185652983df5be276e2 /fpga/usrp3/top/x400/dboards/zbx | |
| parent | 38c549d1f7672e38773fc6624539cc166285a1df (diff) | |
| download | uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.tar.gz uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.tar.bz2 uhd-4bfbb9eeec92fdd3e9d7096006f63477d4848f76.zip | |
fpga: x400: Expand PS GPIO port for DIO control
Diffstat (limited to 'fpga/usrp3/top/x400/dboards/zbx')
| -rw-r--r-- | fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index 0e75b610c..2b765e856 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -854,7 +854,7 @@ set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/r set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ../ctrlport_window.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.v set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys |