From 4bfbb9eeec92fdd3e9d7096006f63477d4848f76 Mon Sep 17 00:00:00 2001 From: Javier Valenzuela Date: Mon, 27 Sep 2021 14:35:57 -0500 Subject: fpga: x400: Expand PS GPIO port for DIO control --- fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/top/x400/dboards/zbx') diff --git a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf index 0e75b610c..2b765e856 100644 --- a/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf +++ b/fpga/usrp3/top/x400/dboards/zbx/cpld/quartus/zbx_top_cpld.qsf @@ -854,7 +854,7 @@ set_global_assignment -name VERILOG_INCLUDE_FILE ../../../../../../lib/control/r set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/ram_2port.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/handshake.v set_global_assignment -name VERILOG_FILE ../../../../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ../ctrlport_window.v +set_global_assignment -name VERILOG_FILE ../../../../../../lib/rfnoc/utils/ctrlport_window.v set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys set_global_assignment -name QSYS_FILE ../ip/osc/osc.qsys -- cgit v1.2.3