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authorMax Köhler <max.koehler@ni.com>2021-02-05 13:14:41 -0600
committerAaron Rossetto <aaron.rossetto@ni.com>2021-06-10 11:56:58 -0500
commit7015f5ed2d495f3908773b7c7d74864d0cc3871a (patch)
treee9c9f7d95f5c35c089bfc9534707934bfe41344a /fpga/usrp3/top/x400/cpld/ip/cmi
parent6d3765605262016a80f71e36357f749ea35cbe5a (diff)
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fpga: x400: cpld: Add support for X410 motherboard CPLD
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com>
Diffstat (limited to 'fpga/usrp3/top/x400/cpld/ip/cmi')
-rw-r--r--fpga/usrp3/top/x400/cpld/ip/cmi/.gitignore2
-rw-r--r--fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.qxpbin0 -> 234390 bytes
-rw-r--r--fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.vhd38
-rw-r--r--fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmiWrapper.vhd93
4 files changed, 133 insertions, 0 deletions
diff --git a/fpga/usrp3/top/x400/cpld/ip/cmi/.gitignore b/fpga/usrp3/top/x400/cpld/ip/cmi/.gitignore
new file mode 100644
index 000000000..f479dbc97
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/cmi/.gitignore
@@ -0,0 +1,2 @@
+# GUI logfile
+PcieCmi.qarlog
diff --git a/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.qxp b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.qxp
new file mode 100644
index 000000000..c03dfd331
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.qxp
Binary files differ
diff --git a/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.vhd b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.vhd
new file mode 100644
index 000000000..8bd0fbb1b
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmi.vhd
@@ -0,0 +1,38 @@
+--
+-- Copyright 2021 Ettus Research, a National Instruments Brand
+--
+-- SPDX-License-Identifier: LGPL-3.0-or-later
+--
+-- Module: PcieCmi
+--
+-- Description:
+--
+-- This is an automatically generated file.
+-- Do not modify this file directly!
+--
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+entity PcieCmi is
+ generic (
+ kSimulation : natural := 0
+ );
+ port (
+ Clk : in std_logic ;
+ acReset : in std_logic ;
+ cSerialNumber : in std_logic_vector (39 downto 0);
+ cBoardIsReady : in std_logic ;
+ cCmiReset : out std_logic ;
+ cOtherSideDetected : out std_logic ;
+ aCblPrsnt_n : in std_logic ;
+ aSdaIn : in std_logic ;
+ aSdaOut : out std_logic ;
+ aSclIn : in std_logic ;
+ aSclOut : out std_logic
+ );
+end entity PcieCmi;
+architecture rtl of PcieCmi is
+begin
+end architecture rtl;
diff --git a/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmiWrapper.vhd b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmiWrapper.vhd
new file mode 100644
index 000000000..2037d10ed
--- /dev/null
+++ b/fpga/usrp3/top/x400/cpld/ip/cmi/PcieCmiWrapper.vhd
@@ -0,0 +1,93 @@
+--
+-- Copyright 2021 Ettus Research, a National Instruments Brand
+--
+-- SPDX-License-Identifier: LGPL-3.0-or-later
+--
+-- Module: PcieCmiWrapper
+--
+-- Description:
+--
+-- This is an automatically generated file.
+-- Do not modify this file directly!
+--
+
+
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+--synopsys translate_off
+--For synthesis, netlist comes from an qxp and there is no external library
+--For simulation in client, netlist comes from PcieCmiLib external library
+--For simulation in dev branch, netlist comes from work library.
+--Binding will work fine in both simulation cases as long as PcieCmi is compiled
+-- to either library. In dev branch PcieCmiLib will be an empty library just so
+-- ModelSim doesn't complain.
+library PcieCmiLib;
+--synopsys translate_on
+
+entity PcieCmiWrapper is
+ generic (
+ kSimulation : natural := 0 -- set to 1 to speedup simulation
+ );
+ port (
+ Clk : in std_logic; -- 40 MHz clock
+ acReset : in std_logic;
+
+ cSerialNumber : in std_logic_vector(39 downto 0);
+ cBoardIsReady : in std_logic;
+ cCmiReset : out std_logic;
+ cOtherSideDetected : out std_logic;
+
+ aCblPrsnt_n : in std_logic;
+
+ aSdaIn : in std_logic;
+ aSdaOut : out std_logic;
+ aSclIn : in std_logic;
+ aSclOut : out std_logic
+ );
+end PcieCmiWrapper;
+
+architecture rtl of PcieCmiWrapper is
+
+ component PcieCmi
+ generic (kSimulation : natural := 0);
+ port (
+ Clk : in std_logic;
+ acReset : in std_logic;
+ cSerialNumber : in std_logic_vector(39 downto 0);
+ cBoardIsReady : in std_logic;
+ cCmiReset : out std_logic;
+ cOtherSideDetected : out std_logic;
+ aCblPrsnt_n : in std_logic;
+ aSdaIn : in std_logic;
+ aSdaOut : out std_logic;
+ aSclIn : in std_logic;
+ aSclOut : out std_logic);
+ end component;
+
+begin
+
+ -- Just forward all signals to lower level entity.
+ -- Leave the simulation generic in place as it important to be able to
+ -- simulate the netlist in reasonable time. For the synthesis in the client
+ -- the generic is ignored as the netlist is translated with kSimulation set to
+ -- default value and "overwrites" it.
+
+ --vhook PcieCmi
+ PcieCmix: PcieCmi
+ generic map (kSimulation => kSimulation) --natural:=0
+ port map (
+ Clk => Clk, --in std_logic
+ acReset => acReset, --in std_logic
+ cSerialNumber => cSerialNumber, --in std_logic_vector(39:0)
+ cBoardIsReady => cBoardIsReady, --in std_logic
+ cCmiReset => cCmiReset, --out std_logic
+ cOtherSideDetected => cOtherSideDetected, --out std_logic
+ aCblPrsnt_n => aCblPrsnt_n, --in std_logic
+ aSdaIn => aSdaIn, --in std_logic
+ aSdaOut => aSdaOut, --out std_logic
+ aSclIn => aSclIn, --in std_logic
+ aSclOut => aSclOut); --out std_logic
+
+end architecture rtl; \ No newline at end of file